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型號(hào)：	S80C32-40SHXXX:RD
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	340/1021頁(yè)
文件大?。?/td>	15196K

32072H–AVR32–10/2012

AT32UC3A3

Interrupts

The GPIO can be configured to generate an interrupt when it detects an input change on an I/O

line. The module can be configured to signal an interrupt whenever a pin changes value or only

to trigger on rising edges or falling edges. Interrupts are enabled on a pin by writing a one to the

corresponding bit in the Interrupt Enable Register (IER). The interrupt mode is set by writing to

the Interrupt Mode Register 0 (IMR0) and the Interrupt Mode Register 1(IMR1). Interrupts can be

enabled on a pin, regardless of the configuration of the I/O line, i.e. whether it is controlled by the

GPIO or assigned to a peripheral function.

In every port there are four interrupt lines connected to the interrupt controller. Groups of eight

interrupts in the port are ORed together to form an interrupt line.

When an interrupt event is detected on an I/O line, and the corresponding bit in IER is written to

one, the GPIO interrupt request line is asserted. A number of interrupt signals are ORed-wired

together to generate a single interrupt signal to the interrupt controller.

The Interrupt Flag Register (IFR) can by read to determine which pin(s) caused the interrupt.

The interrupt bit must be cleared by writing a one to the Interrupt Flag Clear Register (IFRC).

take effect, the clear operation must be performed when the interrupt line is enabled in IER. Oth-

erwise, it will be ignored.

GPIO interrupts can only be triggered when the CLK_GPIO is enabled.

Interrupt Timings

The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter

is disabled. For the pulse to be registered, it must be sampled at the rising edge of the clock. In

this example, this is not the case for the first pulse. The second pulse is however sampled on a

rising edge and will trigger an interrupt request.

Figure 20-4. Interrupt Timing With Glitch Filter Disabled

The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter

is enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges.

In the example, the first pulse is rejected while the second pulse is accepted and causes an

interrupt request.

Figure 20-5. Interrupt Timing With Glitch Filter Enabled

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S80C52XXX-16R	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C32-42	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-42R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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