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型號：	S80C32-40SHXXX:RD
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁數(shù)：	692/1021頁
文件大小：	15196K

32072H–AVR32–10/2012

AT32UC3A3

CURRBK: Current Bank

This bit is set for non-control endpoints, to indicate the current bank:

This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.

NBUSYBK: Number of Busy Banks

This field is set to indicate the number of busy banks:

For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this

triggers an EPnINT interrupt if NBUSYBKE is one.

For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this

triggers an EPnINT interrupt if NBUSYBKE is one.

When the FIFOCON bit is cleared (by writing a one to the FIFOCONC bit) to validate a new bank, this field is updated two or

three clock cycles later to calculate the address of the next bank.

An EPnINT interrupt is triggered if:

- for IN endpoint, NBUSYBKE is one and all the banks are free.

- for OUT endpoint, NBUSYBKE is one and all the banks are busy.

ERRORTRANS: High-bandwidth isochronous OUT endpoint transaction error Interrupt

This bit is set when a transaction error occurs during the current micro-frame (the data toggle sequencing does not respect the

usb 2.0 standard). This triggers an EPnINT interrupt if ERRORTRANSE is one.

This bit is set as long as the current bank (CURRBK) belongs to the bad n-transactions (n=1,2 or 3) transferred during the

micro-frame. Shall be cleared by software by clearing (at least once) the FIFOCON bit to switch to the bank that belongs to the

next n-transactions (next micro-frame).

Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.

DTSEQ: Data Toggle Sequence

This field is set to indicate the PID of the current bank:

For IN transfers, it indicates the data toggle sequence that will be used for the next packet to be sent. This is not relative to the

current bank.

Current Bank

Bank2 if supported

Number of Busy Banks

0 (all banks free)

3 if supported

Data Toggle Sequence

Data2 (for high-bandwidth isochronous endpoint)

MData (for high-bandwidth isochronous endpoint)

相關(guān)PDF資料	PDF描述
S80C52XXX-12:RD	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
SC-80C32E-30/883	8-BIT, 30 MHz, MICROCONTROLLER, CDIP40
S80C52XXX-16R	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
S80C32XXX-40R	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S83C154DXXX-30D	8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C32-42	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-42R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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