955
32072H–AVR32–10/2012
AT32UC3A3
6.
Scan in an 16-bit counter value.
7.
Go to Update-DR and re-enter Select-DR Scan.
8.
In Shift-DR: Scan out the busy bit, and until the busy bit clears goto 7.
9.
Calculate an approximation to the internal clock speed using the elapsed time and the
counter value.
10. Return to Run-Test/Idle.
The full 16-bit counter value must be provided when starting the synch operation, or the result
will be undefined. When reading status, shifting may be terminated once the required number of
bits have been acquired.
35.5.3.8
AVR_RESET
This instruction allows a debugger or tester to directly control separate reset domains inside the
chip. The shift register contains one bit for each controllable reset domain. Setting a bit to one
resets that domain and holds it in reset. Setting a bit to zero releases the reset for that domain.
The AVR_RESET instruction can be used in the following way:
1.
Select the IR Scan path.
2.
In Capture-IR: The IR output value is latched into the shift register.
3.
In Shift-IR: The instruction register is shifted by the TCK input.
4.
Return to Run-Test/Idle.
5.
Select the DR Scan path.
6.
In Shift-DR: Scan in the value corresponding to the reset domains the JTAG master
wants to reset into the data register.
7.
Return to Run-Test/Idle.
8.
Stay in run test idle for at least 10 TCK clock cycles to let the reset propagate to the
system.
See the device specific documentation for the number of reset domains, and what these
domains are.
For any operation, all bits must be provided or the result will be undefined.
Table 35-23. SYNC_ACCESS Details
Instructions
Details
IR input value
10111 (0x17)
IR output value
peb01
DR Size
16 bits
DR input value
dddddddd dddddddd
DR output value
xxxxxxxx xxxxxxeb
Table 35-24. AVR_RESET Details
Instructions
Details
IR input value
01100 (0x0C)
IR output value
p0001