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型號(hào)：	S80C32-40SHXXX:RD
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	409/1021頁(yè)
文件大小：	15196K

32072H–AVR32–10/2012

AT32UC3A3

Power Management

If the CPU enters a sleep mode that disables clocks used by the TWIS, the TWIS will stop func-

tioning and resume operation after the system wakes up from sleep mode.

The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This

clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-

able the TWIS before disabling the clock, to avoid freezing the TWIS in an undefined state.

The TWIS DMA handshake interface is connected to the Peripheral DMA Controller. Using the

TWIS DMA functionality requires the Peripheral DMA Controller to be programmed after setting

up the TWIS.

Interrupts

The TWIS interrupt request lines are connected to the interrupt controller. Using the TWIS inter-

rupts requires the interrupt controller to be programmed first.

Debug Operation

When an external debugger forces the CPU into debug mode, the TWIS continues normal oper-

ation. If the TWIS is configured in a way that requires it to be periodically serviced by the CPU

through interrupts or similar, improper operation or data loss may result during debugging.

Functional Description

Transfer Format

The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must

be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure

Each transfer begins with a START condition and terminates with a STOP condition (see Figure

A high-to-low transition on the TWD line while TWCK is high defines the START condition.

A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.

Figure 22-3.

START and STOP Conditions

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
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