200
ATmega8A [DATASHEET]
8159E–AVR–02/2013
24.8.1
Performing Page Erase by SPM
To execute page erase, set up the address in the Z-pointer, write “X0000011” to SPMCR and execute SPM within
four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to
PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation.
Page Erase to the RWW section: The NRWW section can be read during the page erase.
Page Erase to the NRWW section: The CPU is halted during the operation.
Note:
If an interrupt occurs in the timed sequence the four cycle access cannot be guaranteed. In order to ensure atomic
operation disable interrupts before writing to SPMCSR.
24.8.2
Filling the Temporary Buffer (Page Loading)
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “00000001” to SPMCR
and execute SPM within four clock cycles after writing SPMCR. The content of PCWORD in the Z-register is used
to address the data in the temporary page buffer. The temporary buffer will auto-erase after a page write operation
or by writing the RWWSRE bit in SPMCR. It is also erased after a System Reset. Note that it is not possible to write
more than one time to each address without erasing the temporary buffer.
Note:
If the EEPROM is written in the middle of an SPM page Load operation, all data loaded will be lost.
24.8.3
Performing a Page Write
To execute page write, set up the address in the Z-pointer, write “X0000101” to SPMCR and execute SPM within
four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to
PCPAGE. Other bits in the Z-pointer must be written to zero during this operation.
Page Write to the RWW section: The NRWW section can be read during the page write.
Page Write to the NRWW section: The CPU is halted during the operation.
Note:
If an interrupt occurs in the timed sequence the four cycle access cannot be guaranteed. In order to ensure atomic
operation disable interrupts before writing to SPMCSR.
24.8.4
Using the SPM Interrupt
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in
SPMCR is cleared. This means that the interrupt can be used instead of polling the SPMCR Register in software.
When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt
is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in
“Inter-24.8.5
Consideration While Updating BLS
Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11
unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further soft-
ware updates might be impossible. If it is not necessary to change the Boot Loader software itself, it is
recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software
changes.
24.8.6
Prevent Reading the RWW Section During Self-Programming
During Self-Programming (either page erase or page write), the RWW section is always blocked for reading. The
user software itself must prevent that this section is addressed during the self programming operation. The
RWWSB in the SPMCR will be set as long as the RWW section is busy. During Self-Programming the Interrupt
abled. Before addressing the RWW section after the programming is completed, the user software must clear the
example.