220
ATmega8A [DATASHEET]
8159E–AVR–02/2013
Notes:
1.
tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock Bits commands.
2.
tWLRH_CE is valid for the Chip Erase command.
25.8
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled
to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the
Programming Enable instruction needs to be executed first before program/erase operations can be executed.
dedicated for the internal SPI interface.
25.9
Serial Programming Pin Mapping
Figure 25-7. Serial Programming and Veri
fy Notes:
1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the XTAL1 pin.
2. V
CC - 0.3 < AV
CC < VCC + 0.3, however, AVCC should always be within 2.7 - 5.5V.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the
Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation
turns the content of every memory location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the Serial
Clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
ck < 12MHz, 3 CPU clock cycles for fck 12MHz
High: > 2 CPU clock cycles for f
ck < 12MHz, 3 CPU clock cycles for fck 12MHz
25.9.1
Serial Programming Algorithm
When writing serial data to the ATmega8A, data is clocked on the rising edge of SCK.
When reading data from the ATmega8A, data is clocked on the falling edge of SCK. See
Figure 25-8 for timing
details.
Table 25-14. Pin Mapping Serial Programming
Symbol
Pins
I/O
Description
MOSI
PB3
I
Serial data in
MISO
PB4
O
Serial data out
SCK
PB5
I
Serial clock
VCC
GND
XTAL1
SCK
MISO
MOSI
RESET
PB3
PB4
PB5
+2.7 - 5.5V
AVCC
+2.7 - 5.5V (2)