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參數(shù)資料
| 型號(hào)： | SA9025 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 900 MHz transmit modulator and 2.2 GHz fractional-N synthesizer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 X 1.40 MM, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大小： | 134K |
| 代理商： | SA9025 |
Philips Semiconductors
Objective specification
SA9025
900 MHz transmit modulator and 2.2 GHz
fractional–N synthesizer
1997 Aug 01
11
power control,
÷
M (offset loop), SE (Tx
offset loop synthesizer
enable), DUAL mode, Sleep Mode 1 and Sleep Mode 2.
The data for FDAC is stored by the B word into a temporary register.
When the A word is loaded, the data in this temporary register is
loaded together with the A word into the work registers to avoid false
temporary main synthesizer output caused by changes in fractional
compensation.
The A word contains new data for the main divider. The A word is
loaded into the working registers only when a main divider
synchronization signal is active to avoid phase jumps when
reprogramming the main divider. The synchronization pulse is
generated by the main divider when it has reached its terminal
count, at which time a main divider output pulse is also sent to the
main phase detector. This disables the loading of the A word each
main divider cycle during maximum of (NREF /
REF
) seconds.
Therefore, to be sure that the A word will be correctly loaded, the
STROBE signal must be high for at least (NREF /
REF
) seconds.
When programming the A word, the main charge pumps on output
PHP and PHI are set into the speed–up mode as soon as the A
word is latched into the working registers and remain so as long as
STROBE is held high.
SR01447
DATA
D0
CLOCK
STROBE
CLOCK ENABLED–SHIFT IN DATA
CLOCK
DISABLED
STORE DATA
t
SU
LAST
CLOCK
FIRST
CLOCK
t
SU
t
H
t
SU
D1
D21
D23
D0
VALID DATA CHANGE
Figure 5.
Serial Input Timing Sequence
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