參數(shù)資料
型號: SA9025
廠商: NXP SEMICONDUCTORS
元件分類: 通信及網(wǎng)絡
英文描述: 900 MHz transmit modulator and 2.2 GHz fractional-N synthesizer
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP48
封裝: 7 X 7 X 1.40 MM, PLASTIC, LQFP-48
文件頁數(shù): 13/23頁
文件大?。?/td> 134K
代理商: SA9025
Philips Semiconductors
Objective specification
SA9025
900 MHz transmit modulator and 2.2 GHz
fractional–N synthesizer
1997 Aug 01
13
SR01449
D
Q
CLK
(1)
D
Q
CLK
R
Q
D
V
CC
TX
EN
TEMPORARY REGISTER
SE
SYN
EN
(2)
CLOCK
DATA
WORKING REGISTER
R
Q
STROBE
Q
Q
RCLK
(2)
Figure 6.
Transmit Offset Synthesizer Reset Circuit
In Figure 6, the falling edge of the strobe and address, inverted,
toggles the Q output of flip-flop (1) to a ‘1’ state, enabling the phase
detector, VCO, divide by M, TX
IF
buffer and SSB up-converter.
Approximately 80
μ
s after the synthesizer is locked, the TX
EN
signal
(enabled = 1) turns on the modulator and variable gain amplifier.
The rising edge of TX
EN
has no effect on SYN
EN
, however, the
falling (rising inverted) edge toggles the Q output of D flip-flop (2) to
a ‘0’ state. This disables the synthesizer, modulator and variable
gain amplifier. To insure that slow edges on TX
EN
do not cause
improper operation, the TX
EN
is a Schmitt trigger design.
The address decoder for program word ‘D’ ANDed together with the
strobe is used to load the contents of the temporary register into the
working registers. D flip-flop (3) is used to prevent multiple strobe
and address pulses in the event the address decoder output toggles
on garbage bits during the time the strobe remains in a ‘1’ state.
The temporary register is common to the transmit offset synthesizer,
main channel synthesizer and auxiliary synthesizer.
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