參數(shù)資料
型號(hào): SAA2501H
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Digital Audio Broadcast DAB decoder
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù): 28/52頁(yè)
文件大?。?/td> 206K
代理商: SAA2501H
January 1995
28
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
SAA2501
7.20.7
SAA2501
SETTINGS ITEM
The SAA2501 is configured with the SAA2501 settings. The initial value of the SAA2501 settings after reset is all zeros.
Table 21
SAA2501 settings item; 1 byte (read/write)
Notes
1.
MSEL1 and MSEL0; these bits select the used input interface, the input data format and the input synchronization
type (see Table 22).
CRCACT; automatic/forced CRC activity:
a) CRCACT = 0; the SAA2501 uses the protection bit in the ISO/MPEG frame header to determine the presence of
the CRC.
b) CRCACT = 1; the SAA2501 assumes the CRC always to be present. The protection bit in the used ISO/MPEG
frame header is forced to 0.
MCKDIS; buffered master clock MCLK disabling:
a) MCKDIS = 0; enable MCLK.
b) MCKDIS = 1; disable (3-state) MCLK.
2.
3.
4.
FCKENA; buffered 256f
s
or 384f
s
output signal FSCLK enabling:
a) FCKENA = 0; disable (3-sate) FSCLK.
b) FCKENA = 1; enable FSCLK.
SELCH2; with dual channel mode input data (with other modes of input data ‘don’t care’:
a) SELCH2 = 0; select channel I.
b) SELCH2 = 1; select channel II.
RND1 and RND0; these bits select the rounding of the baseband audio output samples (see Table 23).
5.
6.
Table 22
MSEL1 and MSEL0
Table 23
RND1 and RND0
7
6
5
4
3
2
1
0
MSEL1
(1)
MSEL0
(1)
CRCACT
(2)
MCKDIS
(3)
FCKENA
(4)
SELCH2
(5)
RND1
(6)
RND0
(6)
MSEL1
MSEL0
USED INPUT INTERFACE
INPUT SYNCHRONIZATION
0
0
1
1
0
1
0
1
master
EU147
slave
slave
to ISO/MPEG synchronization pattern
to synchronization signal CDSSY
to ISO/MPEG synchronization pattern
to synchronization signal CDSSY
RND1
RND0
OUTPUT SAMPLE ROUNDING LENGTH
0
0
1
1
0
1
0
1
16 bits
18 bits
20 bits
22 bits
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