參數(shù)資料
型號(hào)： SAA2501H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Digital Audio Broadcast DAB decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 32/52頁(yè)
文件大小： 206K
代理商： SAA2501H
January 1995
32
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
SAA2501
Table 31
APU coefficients item; 4 bytes (write-only); see note 1
Note
1.
Multiple options are supplied by the SAA2501 to increase the timing accuracy of the APU coefficient writing
(see Section 8.2).
SUBSEQUENT
BYTES
7
6
5
4
3
2
1
0
APU coefficient LL
APU coefficient LR
APU coefficient RL
APU coefficient RR
0
0
0
0
LL.6
LR.6
RL.6
RR.6
LL.5
LR.5
RL.5
RR.5
LL.4
LR.4
RL.4
RR.4
LL.3
LR.3
RL.3
RR.3
LL.2
LR.2
RL.2
RR.2
LL.1
LR.1
RL.1
RR.1
LL.0
LR.0
RL.0
RR.0
7.20.13 S
PEED LIMITATIONS OF THE
L3
INTERFACE
When reading the status of, or writing control bytes to the
SAA2501, no status polling is necessary, so the speed of
these transfers is only limited by the maximum frequency
of signal L3CLK and the timing constraints of the L3
protocol.
When reading or writing data item bytes, status polling is
necessary. In addition to the speed limitation this poses,
the application must take precautions that individual data
item bytes are transferred at an interval of at least 200
μ
s.
Neither the status polling nor a minimum interval between
transfers is required when transferring the APU coefficient
item.
7.20.14 D
EFAULT ITEM DATA VALUES AFTER RESET
At a device reset, the L3 interface initialization procedure
must be followed. All writeable data items are pre-loaded
with a defined default value after the device reset signal
has been de-activated. These default values are
summarized in Table 32.
Table 32
SAA2501 settings item; default value after device reset (notes 1 to 6)
Notes
1.
MSEL1 = 0 and MSEL0 = 0; the master input is selected. The SAA2501 synchronizes to the ISO/MPEG
synchronization pattern.
CRCACT = 0; the SAA2501 uses the protection bit in the ISO/MPEG frame header to determine if the CRC is active.
MCKDIS = 0; the buffered master clock output MCLK is enabled.
2.
3.
4.
FCKENA = 0; the buffered 256f
s
or 384f
s
clock output is disabled.
SELCH2 = 0; when decoding input data with dual channel mode, channel I is output on both baseband audio output
channels.
RND1 = 0 and RND0 = 0; the baseband audio output signals are rounded to 16 bit.
5.
6.
SUBSEQUENT
BYTES
7
6
5
4
3
2
1
0
SAA2501 settings
Value
MSEL1
0
MSEL0
0
CRCACT
0
MCKDIS
0
FCKENA
0
SELCH2
0
RND1
0
RND0
0
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