參數(shù)資料
型號(hào): SAA2501H
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Digital Audio Broadcast DAB decoder
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù): 45/52頁
文件大小: 206K
代理商: SAA2501H
January 1995
45
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
SAA2501
FSCLK
f
clk
clock frequency
MSEL = 00;
FSCLKM = 0;
f
s
= 44.1 kHz
MSEL = 00;
FSCLKM = 0;
f
s
= 48 kHz
MSEL = 00;
FSCLKM = 0;
f
s
= 32 kHz
1
2
f
X22IN
MHz
1
2
f
MCLKIN
MHz
1
3
f
MCLKIN
MHz
MCLK
f
clk
clock frequency
f
MCLKIN
MHz
SCK
f
clk
clock frequency
FSCLK384 = 0;
f
SCK
= 64f
s
FSCLK384 = 1;
f
SCK
= 64f
s
1
4
f
SCLK
MHz
1
6
f
SCLK
MHz
Inputs
C
i
t
su1
t
su2
input capacitance
set-up time FDAI to SCK HIGH
set-up time CDM and CDMEF to
CDMCL, CDS, CDSEF and CDSWA
HIGH
set-up time CDSSY to CDSCL HIGH
delay time L3MODE to L3LCK LOW
hold time FDAI to SCK HIGH
hold time CDM, CDMEF to CDMCL,
CDS, CDSEF and CDSWA HIGH
hold time CDSSY to CDSCL HIGH
input hold time
L3MODE LOW time
33
42
10
pF
ns
ns
C
L
< 25 pF
C
L
< 25 pF
t
su3
t
d1
t
h1
t
h2
T
m
+ 10
0
0
0
ns
ns
ns
ns
t
h3
t
h4
t
L
10
0
T
m
+ 10
ns
ns
ns
Outputs
C
o
t
h
output capacitance
hold time SD, WS, FDAO, FDFSY and
FDEF to SCK LOW
hold time CDMWS to CDMCL LOW
delay time SD, WS, FDAO, FDFSY and
FDEF to CDMCL LOW
delay time CDMWS to CDMCL LOW
22
50
pF
ns
notes 3 and 4
t
h
t
d
notes 3 and 4
note 3
15
10
ns
ns
t
d
note 3
0
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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