參數(shù)資料
型號： SAA55XX
廠商： NXP Semiconductors N.V.
英文描述： TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD)
中文描述： 與隱藏字幕（CC）和屏幕顯示（OSD電視微控制器）
文件頁數(shù)： 10/84頁
文件大?。?/td> 352K
代理商： SAA55XX
2000 Feb 23
10
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
7
MICROCONTROLLER
The functionality of the microcontroller used on this device
is described here with reference to the industry standard
80C51 microcontroller. A full description of its functionality
can be found in the “Handbook IC20, 80C51-Based 8-bit
Microcontrollers”
7.1
Microcontroller features
80C51 microcontroller core standard instruction set and
timing
1
μ
s machine cycle
Maximum 64K
×
8-bit program ROM
2
×
8-bit auxiliary RAM, maximum of 1.25 kbytes
required for display
Interrupt controller for individual enable/disable with two
level priority
Two 16-bit timer/counter registers
Watchdog Timer
Auxiliary RAM page pointer
16-bit data pointer
Standby, Idle and Power-down modes
29 general I/O lines
Eight 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analog signals
One 14-bit PWM for Voltage Synthesis Tuner (VST)
control
8-bit Analog-to-Digital Converter (ADC) with four
multiplexed inputs
2 high current outputs for directly driving LEDs
I
2
C-bus byte level bus interface with dual ports.
8
MEMORY ORGANIZATION
The device has the capability of a maximum of 64-kbyte
Program ROM and 2-kbyte Data RAM internally.
8.1
ROM bank switching
As the Program ROM does not exceed 64 kbytes in any of
the OSD only variants, ROM bank switching is not
required.
The memory and security bits are structured as shown in
Fig.4.
The OSD only security bits are set as shown in Fig.5 for
production programmed devices.
The OSD only security bits are set as shown in Fig.6 for
production blank devices.
8.2
RAM organisation
The Internal Data RAM is organized into two areas, Data
memory and Special Function Registers (SFRs).
8.3
Data memory
TheDatamemoryis256
×
8-bit,andoccupiestheaddress
range 00H to FFH when using indirect addressing and
00H to 7FH when using direct addressing. The SFRs
occupy the address range 80H to FFH and are accessible
using direct addressing only.
The lower 128 bytes of Data memory are mapped as
shown in Fig.8.
The lowest 24 bytes are grouped into 4 banks of
8 registers, the next 16 bytes above the register banks
form a block of bit addressable memory space.
The upper 128 bytes are not allocated for any special area
or functions.
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