參數(shù)資料
型號(hào)： SAA55XX
廠商： NXP Semiconductors N.V.
英文描述： TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD)
中文描述： 與隱藏字幕（CC）和屏幕顯示（OSD電視微控制器）
文件頁數(shù)： 37/84頁
文件大?。?/td> 352K
代理商： SAA55XX
2000 Feb 23
37
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
15 I
2
C-BUS SERIAL I/O
The I
2
C-bus consists of a serial data (SDA) line and a
serial clock (SCL) line. The definition of the I
2
C-bus
protocol can be found in the document “The I
2
C-bus and
how to use it (including specification)”. This document may
be ordered using the code 9398 393 40011.
The device operates in four modes:
Master transmitter
Master receiver
Slave transmitter
Slave receiver.
The microcontroller peripheral is controlled by the Serial
Control SFR (S1CON) and its status is indicated by the
Status SFR (S1STA). Information is transmitted/received
to/from the I
2
C-bus using the Data SFR (S1DAT) and the
Slave Address SFR (S1ADR) is used to configure the
slave address of the peripheral.
The byte level I
2
C-bus serial port is identical to the I
2
C-bus
serial port on the P8xCE558, except for the clock rate
selection bits CR<2:0> in S1CON. The operation of the
subsystem is described in detail in the “P8xCE558 data
sheet”
15.1
I
2
C-bus port selection
Two I
2
C-bus ports are available SCL0/SDA0 and
SCL1/SDA1. The selection of the port is done using
TXT21.I
2
C PORT 0 and TXT21.I
2
C PORT 1. When the
port is enabled, any information transmitted from the
device goes onto the enabled port. Any information
transmitted to the device can only be acted on if the port is
enabled.
If both ports are enabled then data transmitted from the
device is seen on both ports, however data transmitted to
the device on one port can not be seen on the other port.
16 MEMORY INTERFACE
The memory interface controls access to the embedded
DRAM, refreshing of the DRAM and page clearing.
The DRAM is shared between Data Capture, display and
microcontroller sections.
The Data Capture section uses the DRAM to store
acquired information that has been requested. The display
readsfromthe DRAMinformation and convertsit intoRGB
values. The microcontroller uses the DRAM as embedded
auxiliary RAM.
16.1
Memory structure
The memory is partitioned into two distinct areas, the
dedicated Auxiliary RAM area, and the Display RAM area.
The Display RAM area when not being used for Data
Capture or Display can be used as an extension to the
auxiliary RAM area.
16.1.1
A
UXILIARY
RAM
The Auxiliary RAM is not initialised at power-up.
ApplicationsoftwaremustinitializethisAuxiliaryRAM.The
contents of the Auxiliary RAM area, and the Display RAM
are maintained during Standby and Idle modes, but are
lost if Power-down mode is entered.
16.1.2
D
ISPLAY
RAM
The Display RAM (Block 0 only) is initialised on power-up
to a value of 20H. The contents of the Display RAM are
maintained when entering Idle mode. If Idle mode is exited
using an interrupt then the contents are unchanged, if Idle
mode is exited using a reset then the contents are
re-initialised to 20H.
Full Closed Caption display requires a display RAM from
8000H to 845FH. The memory from 8460H to 84FFH
(must be initialized by the application software) can be
utilized as an extension to the dedicated contiguous
Auxiliary RAM that occupies 000H to 02FFH.
16.2
Memory mapping
The dedicated Auxiliary RAM area occupies 0.75 kbytes,
with an address range from 0000H to 02FFH. The Display
RAM occupies 1.25 kbytes with an address range from
2000H to 24FFH for TXT mode and 8000H to 84FFH for
CC mode. The two modes although having different
address ranges occupy the same physical DRAM area.
The hardware will only initialize 1-kbyte (block 0) of the
available 1.25 kbytes on the device. The application
software must initialize this additional 0.25 kbytes if it is to
be used as display RAM or auxiliary RAM.
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