參數(shù)資料
型號(hào)： SAA55XX
廠商： NXP Semiconductors N.V.
英文描述： TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD)
中文描述： 與隱藏字幕（CC）和屏幕顯示（OSD電視微控制器）
文件頁(yè)數(shù)： 32/84頁(yè)
文件大小： 352K
代理商： SAA55XX
2000 Feb 23
32
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
11 INTERRUPT SYSTEM
The device has six interrupt sources, each of which can be
enabled or disabled. When enabled each interrupt can be
assigned one of two priority levels. There are four
interrupts that are common to the 80C51, two of these are
external interrupts (EX0 and EX1) and the other two are
timer interrupts (ET0 and ET1). In addition to the
conventional 80C51, one application specific interrupt is
incorporated internal to the device which has following
functionality:
Display Busy interrupt (EBUSY).
An interrupt is
generated when the display enters either a Horizontal or
Vertical Blanking Period. i.e. indicates when the
microcontroller can update the display RAM without
causing undesired effects on the screen. This interrupt
can be configured in one of two modes using the MMR
Configuration (address 87FFH, bit TXT/V):
– Text Display Busy. An interrupt is generated on each
active horizontal display line when the Horizontal
Blanking Period is entered
– Vertical Display Busy. An interrupt is generated on
each vertical display field when the Vertical Blanking
period is entered.
11.1
Interrupt enable structure
Each of the individual interrupts can be enabled or
disabled by setting or clearing the relevant bit in the
Interrupt Enable Register (IE). All interrupt sources can
also be globally disabled by clearing the EA bit (IE.7).
11.2
Interrupt enable priority
Each interrupt source can be assigned one of two priority
levels. The interrupt priorities are defined by the Interrupt
Priority Register (IP). A low priority interrupt can be
interrupted by a high priority interrupt, but not by another
low priority interrupt. A high priority interrupt can not be
interrupted by any other interrupt source. If two requests of
different priority level are received simultaneously, the
request with the highest priority level is serviced.
If requests of the same priority level are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level
there is a second priority structure determined by the
polling sequence as defined in Table 8.
Table 8
Interrupt priority (within same level)
11.3
Interrupt vector address
The processor acknowledges an interrupt request by
executing a hardware generated LCALL to the appropriate
servicing routine. The interrupt vector addresses for each
source are shown in Table 8.
11.4
Level/edge interrupt
The external interrupt can be programmed to be either
level-activated or transition-activated by setting or clearing
the IT0/IT1 bits in the Timer Control SFR (TCON).
Table 9
External interrupt activation
The external interrupt INT1 differs from the standard
80C51 interrupt in that it is activated on both edges when
in edge sensitive mode. This is to allow software pulse
width measurement for handling remote control inputs.
SOURCE
PRIORITY WITHIN
LEVEL
INTERRUPT
VECTOR
EX0
ET0
EX1
ET1
ES2
EBUSY
highest
lowest
0003H
000BH
0013H
001BH
002BH
0033H
ITx
LEVEL
EDGE
0
1
active LOW
INT0 = negative edge
INT1 = positive and negative edge
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