2004 Mar 16
11
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
FSVGC
SDAe
CBO
PIXCLKO
V
DDEd
IGPH
IGP1
ITRI
PD2
G1
G2
G3
G4
G11
G12
G13
G14
H1
I/O
I/O
O
O
S
O
O
I/(O)
I
frame synchronization output to VGC (optional input)
I
2
C-bus serial data input/output (encoder)
composite blanking output to VGC; active LOW
pixel clock output to VGC
3.3 V digital supply voltage for peripheral cells (decoder)
multi-purpose horizontal reference output with IPD output bus
general purpose output signal 1 with IPD output bus
programmable control signals for IPD output bus
MSB
5 of encoder input bus with C
B
-Y-C
R
4 : 2 : 2; see Tables 25 to 31 for
pin assignment
MSB
6 of encoder input bus with C
B
-Y-C
R
4 : 2 : 2; see Tables 25 to 31 for
pin assignment
MSB
7 of encoder input bus with C
B
-Y-C
R
4 : 2 : 2; see Tables 25 to 31 for
pin assignment
digital ground for peripheral cells (decoder)
digital ground for peripheral cells (decoder)
clock for IPD output bus (optional clock input)
scan test output, do not connect
data qualifier for IPD output bus
scan test output, do not connect
scan test input, do not connect
scan test input, do not connect
3.3 V digital supply voltage for core (decoder)
3.3 V digital supply voltage for core (decoder)
audio master external clock input
audio left/right clock output; can be strapped to supply via a 3.3 k
resistor to
indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down)
has been replaced by a 32.110 MHz crystal (ALRCLK = 1); notes 5 and 6
target ready input for IPD output bus
control signal for all X port pins
MSB of XPD bus
MSB
1 of XPD bus
digital ground core (decoder)
digital ground core (decoder)
audio master clock output, must be less than 50% of crystal clock
real-time status or sync information line 0
audio serial clock output
MSB
2 of XPD bus
MSB
3 of XPD bus
MSB
4 of XPD bus
3.3 V digital supply voltage for core (decoder)
vertical reference for XPD bus
PD1
H2
I
PD0
H3
I
V
SSEd
V
SSEd
ICLK
TEST0
IDQ
TEST4
TEST5
TEST3
V
DDId
V
DDId
AMXCLK
ALRCLK
H4
H11
H12
H13
H14
J1
J2
J3
J4
J11
J12
J13
S
S
I/O
O
O
O
I
I
S
S
I
(I/)O
ITRDY
XTRI
XPD7
XPD6
V
SSId
V
SSId
AMCLK
RTS0
ASCLK
XPD5
XPD4
XPD3
V
DDId
XRV
J14
K1
K2
K3
K4
K11
K12
K13
K14
L1
L2
L3
L4
L5
I
I
I/O
I/O
S
S
O
O
O
I/O
I/O
I/O
S
I/O
SYMBOL
PIN
TYPE
(1)
DESCRIPTION