參數(shù)資料
型號(hào): SAA7108E
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: PC-CODEC
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA156
封裝: 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, SOT-472-1, BGA-156
文件頁數(shù): 69/202頁
文件大小: 983K
代理商: SAA7108E
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2004 Mar 16
69
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
9.3
Scaler
The High Performance video Scaler (HPS) is based on the
system as implemented in the SAA7140, but enhanced in
some aspects. Vertical upsampling is supported and the
processing pipeline buffer capacity is enhanced, to allow
more flexible video stream timing at the image port,
discontinuous transfers and handshake. The internal data
flow from block to block is discontinuous dynamically, due
to the scaling process.
The flow is controlled by internal data valid and data
request flags (internal handshake signalling) between the
sub-blocks. Therefore the entire scaler acts as a pipeline
buffer. Depending on the actually programmed scaling
parameters the effective buffer can exceed to an entire
line. The access/bandwidth requirements to the VGA
frame buffer are reduced significantly.
The high performance video scaler in the SAA7108E;
SAA7109E has the following major blocks.
Acquisition control (horizontal and vertical timer) and
task handling (the region/field/frame based processing)
Prescaler, for horizontal downscaling by an integer
factor, combined with appropriate band limiting filters,
especially anti-aliasing for CIF format
Brightness, saturation and contrast control for scaled
output data
Line buffer, with asynchronous read and write, to
support vertical upscaling (e.g. for videophone
application, converting 240 into 288 lines, Y-C
B
-C
R
4 : 2 : 2)
Vertical scaling, with phase accurate Linear Phase
Interpolation (LPI) for zoom and downscaling, or phase
accurate Accumulation Mode (ACM) for large
downscaling ratios and better anti-alias suppression
Variable Phase Delay (VPD), operates as horizontal
phase accurate interpolation for arbitrary non-integer
scaling ratios, supporting conversion between square
and rectangular pixel sampling
Output formatter for scaled Y-C
B
-C
R
4 : 2 : 2,
Y-C
B
-C
R
4 : 1 : 1 and Y only (format also for raw data)
FIFO, 32-bit wide, with 64 pixel capacity in Y-C
B
-C
R
formats
Output interface, 8 or 16-bit (only if extended by H port)
data pins wide, synchronous or asynchronous
operation, with stream events on discrete pins, or coded
in the data stream.
The overall H and V zooming (HV_zoom) is restricted by
the input/output data rate relationships. With a safety
margin of 2% for running in and running out, the maximum
HV_zoom is equal to:
in_lines
×
out_cycle_per_pix
×
For example:
1.
Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit
data at 13.5 MHz data rate, 1 cycle per pixel; output:
8-bit data at 27 MHz, 2 cycles per pixel; the maximum
HV_zoom is equal to:
20 ms
24
64
μ
×
288
×
2
×
37 ns
×
2.
Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit
data at 27 MHz data rate (ITU 656), 2 cycles per pixel;
output via I + H port: 16-bit data at 27 MHz clock,
1 cycle per pixel; the maximum HV_zoom is equal to:
22
64
μ
s
×
720
240
×
1
×
37 ns
×
The video scaler receives its input signal from the video
decoder or from the expansion port (X port). It gets 16-bit
Y-C
B
-C
R
4 : 2 : 2 input data at a continuous rate of
13.5 MHz from the decoder. A discontinuous data stream
can be accepted from the expansion port, normally 8-bit
wide ITU 656 like Y-C
B
-C
R
data, accompanied by a pixel
qualifier on XDQ.
The input data stream is sorted into two data paths, one for
luminance (or raw samples), and one for time multiplexed
chrominance C
B
and C
R
samples. A Y-C
B
-C
R
4 : 1 : 1
input format is converted to 4 : 2 : 2 for the horizontal
prescaling and vertical filter scaling operation.
Thescaleroperationisdefinedbytwoprogrammingpages
A and B, representing two different tasks that can be
applied field alternating or to define two regions in a field
(e.g. with different scaling range, factors, and signal
source during odd and even fields).
Each programming page contains control for:
Signal source selection and formats
Task handling and trigger conditions
Input and output acquisition window definition
H prescaler, V scaler and H phase scaling.
Raw VBI data will be handled as specific input format and
need its own programming page (equals own task).
0.98
T_v_blanking
T_out_clk
×
in_pixel
×
0.98
720
1.18
=
×
0.98
16.666 ms
2.34
=
×
相關(guān)PDF資料
PDF描述
SAA7109E PC-CODEC
SAA7108AE HD-CODEC
SAA7109A HD-CODEC
SAA7109AE HD-CODEC
SAA7110A Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7109 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC
SAA7109A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC
SAA7109AE 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC
SAA7109AE/V1,518 功能描述:視頻 IC HD- VIDEO CODEC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
SAA7109AE/V1,557 功能描述:視頻 IC HD- VIDEO CODEC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel