參數(shù)資料
型號(hào): SAK-TC1762-128F80HL
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP176
封裝: PLASTIC, LQFP-176
文件頁數(shù): 41/114頁
文件大?。?/td> 852K
代理商: SAK-TC1762-128F80HL
TC1762
Functional Description
Preliminary
Data Sheet
28
V1.0, 2008-04
3.4
Memory Protection System
The TC1762 memory protection system specifies the addressable range and read/write
permissions of memory segments available to the current executing task. The memory
protection system controls the position and range of addressable segments in memory.
It also controls the types of read and write operations allowed within addressable
memory segments. Any illegal memory access is detected by the memory protection
hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the
error. Thus, the memory protection system protects critical system functions against both
software and hardware errors. The memory protection hardware can also generate
signals to the Debug Unit to facilitate tracing illegal memory accesses.
There are two Memory Protection Register Sets in the TC1762, numbered 0 and 1,
which specify memory protection ranges and permissions for code and data. The
PSW.PRS bit field determines which of these is the set currently in use by the CPU. As
the TC1762 uses a Harvard-style memory architecture, each Memory Protection
Register Set is broken down into a Data Protection Register Set and a Code Protection
Register Set. Each Data Protection Register Set can specify up to four address ranges
to receive a particular protection modes. Each Code Protection Register Set can specify
up to two address ranges to receive a particular protection modes.
Each Data Protection Register Sets and Code Protection Register Sets determines the
range and protection modes for a separate memory area. Each set contains a pair of
registers which determine the address range (the Data Segment Protection Registers
and Code Segment Protection Registers) and one register (Data Protection Mode
Register) which determines the memory access modes that applies to the specified
range.
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