參數(shù)資料
型號: SAK-TC1762-128F80HL
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP176
封裝: PLASTIC, LQFP-176
文件頁數(shù): 66/114頁
文件大?。?/td> 852K
代理商: SAK-TC1762-128F80HL
TC1762
Functional Description
Preliminary
Data Sheet
51
V1.0, 2008-04
Selectable, programmable anti-aliasing and data reduction filter block
3.15
System Timer
The TC1762’s STM is designed for global system timing applications requiring both high
precision and long period.
Features
Free-running 56-bit counter
All 56 bits can be read synchronously
Different 32-bit portions of the 56-bit counter can be read synchronously
Flexible interrupt generation based on compare match with partial STM content
Driven by maximum 66 or 80 MHz (=
f
SYS, default after reset = fSYS/2) depending on
derivative
Counting starts automatically after a reset operation
STM is reset by:
– Watchdog reset
– Software reset (RST_REQ.RRSTM must be set)
– Power-on reset
STM (and clock divider STM_CLC.RMC) is not reset at a hardware reset (HDRST =
0)
STM can be halted in debug/suspend mode (via STM_CLC register)
The STM is an upward counter, running either at the system clock frequency
f
SYS or at a
fraction of it. The STM clock frequency is
f
STM = fSYS/RMC with RMC = 0-7 (default after
reset is
f
STM = fSYS/2, selected by RMC = 010B). RMC is a bit field in register STM_CLC.
In case of a power-on reset, a watchdog reset, or a software reset, the STM is reset. After
one of these reset conditions, the STM is enabled and immediately starts counting up. It
is not possible to affect the content of the timer during normal operation of the TC1762.
The timer registers can only be read but not written to.
The STM can be optionally disabled for power-saving purposes, or suspended for
debugging purposes via its clock control register. In suspend mode of the TC1762
(initiated by writing an appropriate value to STM_CLC register), the STM clock is
stopped but all registers are still readable.
Due to the 56-bit width of the STM, it is not possible to read its entire content with one
instruction. It needs to be read with two load instructions. Since the timer would continue
to count between the two load operations, there is a chance that the two values read are
not consistent (due to possible overflow from the low part of the timer to the high part
between the two read operations). To enable a synchronous and consistent reading
operation of the STM content, a capture register (STM_CAP) is implemented. It latches
the content of the high part of the STM each time when one of the registers STM_TIM0
to STM_TIM5 is read. Thus, STM_CAP holds the upper value of the timer at exactly the
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