參數(shù)資料
型號(hào)： SC16C2550IN40,112
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 11/46頁(yè)
文件大小： 0K
描述： IC UART DUAL W/FIFO 40-DIP
標(biāo)準(zhǔn)包裝： 9
特點(diǎn)： 2 通道
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
電源電壓： 2.5V，3.3V，5V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-DIP
包裝： 管件
其它名稱： 568-3262-5
935270024112
SC16C2550IN40
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
19 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.2.2
IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C2550 in the FIFO
polled mode of operation. In this mode, interrupts are not generated and the user
must poll the LSR register for TX and/or RX data status. Since the receiver and
transmitter have separate bits in the LSR either or both can be used in the polled
mode by selecting respective transmit or receive control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1-4] will provide the type of receive errors, or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
LSR[7] will show if any FIFO data errors occurred.
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
7.3.1
DMA mode
Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) on
PLCC44 and LQFP48 packages will go to a logic 0 whenever the FIFO (THR, if FIFO
is not enabled) is empty. Receive Ready (RXRDY) on PLCC44 and LQFP48
packages will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded
with a character.
Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The
transmit interrupt is set when the transmit FIFO is empty. TXRDY on PLCC and
LQFP48 packages remains a logic 0 as long as one empty FIFO location is available.
The receive interrupt is set when the receive FIFO lls to the programmed trigger
level. However, the FIFO continues to ll regardless of the programmed level until the
FIFO is full. RXRDY on PLCC44 and LQFP48 packages transitions LOW when the
FIFO reaches the trigger level, and transitions HIGH when the FIFO empties.
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