參數(shù)資料
型號： SC16C2550IN40,112
廠商： NXP Semiconductors
文件頁數(shù)： 9/46頁
文件大小： 0K
描述： IC UART DUAL W/FIFO 40-DIP
標(biāo)準(zhǔn)包裝： 9
特點(diǎn)： 2 通道
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
電源電壓： 2.5V，3.3V，5V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-DIP
包裝： 管件
其它名稱： 568-3262-5
935270024112
SC16C2550IN40
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
17 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the TSR and UART via the THR, providing that the THR is empty. The THR empty
ag in the LSR register will be set to a logic 1 when the transmitter is empty or when
data is transferred to the TSR. Note that a write operation can be performed when the
THR empty ag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR
empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and
a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2550
and receive FIFO by reading the RHR register. The receive section provides a
mechanism to prevent false starts. On the falling edge of a start or false start bit, an
internal receiver counter starts counting clocks at the 16
× clock rate. After 7-12
clocks, the start bit time should be shifted to the center of the start bit. At this time the
start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. Receiver status
codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INTA, INTB output pins.
Table 8:
Interrupt Enable Register bits description
Bit
Symbol
Description
7
IER[7]
CTS interrupt.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt. The SC16C2550 issues an
interrupt when the CTS pin transitions from a logic 0 to a logic 1.
6
IER[6]
RTS interrupt.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt. The SC16C2550 issues an
interrupt when the RTS pin transitions from a logic 0 to a logic 1.
5
IER[5]
Xoff interrupt.
Logic 0 = Disable the software ow control, receive Xoff interrupt
(normal default condition).
Logic 1 = Enable the software ow control, receive Xoff interrupt.
4
IER[4]
Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode.
3
IER[3]
Modem Status Interrupt. This interrupt will be issued whenever
there is a modem status change as reected in MSR[0-3].
Logic 0 = Disable the modem status register interrupt (normal
default condition).
Logic 1 = Enable the modem status register interrupt.
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