參數(shù)資料
型號(hào)： SC16C2550IN40,112
廠商： NXP Semiconductors
文件頁數(shù)： 14/46頁
文件大?。?/td> 0K
描述： IC UART DUAL W/FIFO 40-DIP
標(biāo)準(zhǔn)包裝： 9
特點(diǎn)： 2 通道
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
電源電壓： 2.5V，3.3V，5V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-DIP
包裝： 管件
其它名稱： 568-3262-5
935270024112
SC16C2550IN40
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
21 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.4 Interrupt Status Register (ISR)
The SC16C2550 provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. A lower level interrupt may be seen after
servicing the higher level interrupt and re-reading the interrupt status bits. Table 11
“Interrupt source” shows the data values (bits 0-3) for the four prioritized interrupt
levels and the interrupt sources associated with each of these interrupt levels.
1
FCR[1]
RCVR FIFO reset.
Logic 0 = Receive FIFO not reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the
FIFO counter logic (the receive shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFOs enabled.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must
be a ‘1’ when other FCR bits are written to, or they will not
be programmed.
Table 10:
RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level
0001
0104
1008
1114
Table 9:
FIFO Control Register bits description…continued
Bit
Symbol
Description
Table 11:
Interrupt source
Priority
level
ISR[5]
ISR[4]
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0
00110LSR (Receiver Line Status
Register)
2
0
00100
RXRDY (Received Data
Ready)
2
0
01100
RXRDY (Receive Data
time-out)
3
0
00010
TXRDY (Transmitter
Holding Register Empty)
4
0
00000
MSR (Modem Status
Register)
5
0
10000
RXRDY (Received Xoff
signal) / Special character
6
1
00000CTS, RTS change of state
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