參數(shù)資料
型號: SC16C2550IN40,112
廠商: NXP Semiconductors
文件頁數(shù): 3/46頁
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 40-DIP
標準包裝: 9
特點: 2 通道
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應商設備封裝: 40-DIP
包裝: 管件
其它名稱: 568-3262-5
935270024112
SC16C2550IN40
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
11 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.3 FIFO operation
The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control
Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 6-7, but
not the transmit trigger level. The receiver FIFO section includes a time-out function
to ensure data is delivered to the external CPU. An interrupt is generated whenever
the Receive Holding Register (RHR) has not been read following the loading of a
character or the receive trigger level has not been reached.
6.4 Hardware ow control
When automatic hardware ow control is enabled, the SC16C2550 monitors the CTS
pin for a remote buffer overow indication and controls the RTS pin for local buffer
overows. Automatic hardware ow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
ow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C2550 will suspend TX transmissions as soon as the stop bit of the character in
process is shifted out. Transmission is resumed after the CTS input returns to a
logic 0, indicating more data may be sent.
With the Auto RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger. However, under the above described conditions, the
SC16C2550 will continue to accept data until the receive FIFO is full.
6.5 Software ow control
When software ow control is enabled, the SC16C2550 compares one or two
sequential receive data characters with the programmed Xon/Xoff or Xoff1,2
character value(s). If received character(s) match the programmed values, the
SC16C2550 will halt transmission (TX) as soon as the current character(s) has
completed transmission. When a match occurs, the receive ready (if enabled via Xoff
IER[5]) ags will be set and the interrupt output pin (if receive interrupt is enabled) will
be activated. Following a suspension due to a match of the Xoff characters’ values,
the SC16C2550 will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C2550 will resume operation and
clear the ags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit ow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software ow
control. Different conditions can be set to detect Xon/Xoff characters and
suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,
Table 5:
Flow control mechanism
Selected trigger level
(characters)
INT pin activation
Negate RTS or
send Xoff
Assert RTS or
send Xon
11
4
1
44
8
4
8
12
8
14
10
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