參數(shù)資料
型號(hào): SC16C2550IN40,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 2/46頁(yè)
文件大小: 0K
描述: IC UART DUAL W/FIFO 40-DIP
標(biāo)準(zhǔn)包裝: 9
特點(diǎn): 2 通道
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-DIP
包裝: 管件
其它名稱: 568-3262-5
935270024112
SC16C2550IN40
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
10 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.2 Internal registers
The SC16C2550 provides two sets of internal registers (A and B) consisting of
12 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in Table 4. The UART registers function as data
holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO
control register (FCR), line status and control registers (LCR/LSR), modem status
and control registers (MCR/MSR), programmable data rate (clock) control registers
(DLL/DLM), and a user accessible scratchpad register (SPR).
[1]
These registers are accessible only when LCR[7] is a logic 0.
[2]
These registers are accessible only when LCR[7] is a logic 1.
[3]
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
‘BF(HEX)’.
Table 3:
Serial port selection
Chip Select
Function
CSA-CSB = 1
none
CSA = 0
UART channel A
CSB = 0
UART channel B
Table 4:
Internal registers decoding
A2
A1
A0
READ mode
WRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]
0
Receive Holding Register
Transmit Holding Register
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
Line Control Register
1
0
Modem Control Register
1
0
1
Line Status Register
n/a
1
0
Modem Status Register
n/a
1
Scratchpad Register
Baud rate register set (DLL/DLM)[2]
0
LSB of Divisor Latch
0
1
MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)[3]
0
1
0
Enhanced Feature Register
1
0
Xon1 word
1
0
1
Xon2 word
1
0
Xoff1 word
1
Xoff2 word
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