參數(shù)資料
型號(hào)： SCC68692E1F40
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Dual asynchronous receiver/transmitter DUART
中文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CDIP40
文件頁(yè)數(shù)： 14/30頁(yè)
文件大?。?/td> 193K
代理商： SCC68692E1F40
Philips Semiconductors
Product specification
SCC68692
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
14
Table 2.
Register Bit Formats
BIT 7
RxRTS
CONTROL
BIT 6
RxINT
SELECT
BIT 5
ERROR
MODE*
BIT 4 BIT 3
BIT 2
PARITY
TYPE
BIT 1 BIT 0
BITS PER
CHARACTER
00 = 5
01 = 6
10 = 7
11 = 8
MR1A
MR1B
PARITY MODE
0 = No
1 = Yes
0 = RxRDY
1 = FFULL
0 = Char
1 = Block
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
0 = Even
1 = Odd
NOTE:
*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
BIT 7 BIT 6
BIT 5
TxRTS
CONTROL
BIT 4
CTS
BIT 3 BIT 2 BIT 1 BIT 0
MR2A
MR2B
CHANNEL MODE
ENABLE Tx
STOP BIT LENGTH*
00 = Normal
01 = Auto-Echo
10 = Local loop
11 = Remote loop
0 = No
1 = Yes
0 = No
1 = Yes
0 = 0.563
1 = 0.625
2 = 0.688
3 = 0.750
4 = 0.813
5 = 0.875
6 = 0.938
7 = 1.000
8 = 1.563
9 = 1.625
A = 1.688
B = 1.750
C = 1.813
D = 1.875
E = 1.938
F = 2.000
NOTE:
*Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.
CSRA
CSRB
BIT 7 BIT 6 BIT 5 BIT 4
RECEIVER CLOCK SELECT
See Text
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B”in application notes elsewhere in this publication
BIT 3 BIT 2 BIT 1 BIT 0
TRANSMITTER CLOCK SELECT
See Text
BIT 7
BIT 6 BIT 5 BIT 4
MISCELLANEOUS COMMANDS
BIT 3
BIT 2
BIT 1
BIT 0
CRA
CRB
DISABLE Tx
0 = No
1 = Yes
ENABLE Tx
0 = No
1 = Yes
DISABLE Rx
0 = No
1 = Yes
ENABLE Rx
0 = No
1 = Yes
See Text
NOTE:
Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.
BIT 7
BIT 6
FRAMING
ERROR*
0 = No
1 = Yes
BIT 5
PARITY
ERROR*
0 = No
1 = Yes
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SRA
SRB
RECEIVED
BREAK*
0 = No
1 = Yes
OVERRUN
ERROR
0 = No
1 = Yes
TxEMT
TxRDY
FFULL
RxRDY
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
NOTE:
*These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits
(7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are
discarded when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using
the error reset command (command 4x) or a receiver reset.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3 BIT 2
BIT 1 BIT 0
OP7
OP6
OP5
OP4
OP3
OP2
OPCR
0 = OPR[7]
1 = TxRDYB
0 = OPR[6]
1 = TxRDYA
0 = OPR[5]
1 = RxRDY/
FFULLB
0 = OPR[4]
1 = RxRDY/
FFULLA
00 = OPR[3]
01 = C/T OUTPUT
10 = TxCB(1x)
11 = RxCB(1x)
00 = OPR[2]
01 = TxCA(16x)
10 = TxCA(1x)
11 = RxCA(1x)
OPR
OPR bit
OP pin
NOTE:
The level at the OP pin is the inverse of the bit in the OPR register.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
BIT 7
BIT 6 BIT 5 BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BRG SET
SELECT
COUNTER/TIMER
MODE AND SOURCE
DELTA
IP3 INT
DELTA
IP2 INT
DELTA
IP1 INT
DELTA
IP0 INT
ACR
0 = set 1
1 = set 2
See Table 4
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
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