參數(shù)資料
型號: SCC68692E1F40
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Dual asynchronous receiver/transmitter DUART
中文描述: 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CDIP40
文件頁數(shù): 20/30頁
文件大小: 193K
代理商: SCC68692E1F40
Philips Semiconductors
Product specification
SCC68692
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
20
potential problems which may occur if a carry from the lower 8 bits
to the upper 8 bits occurs between the times that both halves of the
counter are read. However, note that a subsequent start counter
command will cause the counter to begin a new count cycle using
the values in CTUR and CTLR.
IVR – Interrupt Vector Register
This register contains the interrupt vector. The register is initialized
to H‘0F’ by RESET. The contents of the register are placed on the
data bus when the DUART responds to a valid interrupt
acknowledge cycle.
SD00028
RESET
t
RES
Figure 3. Reset Timing
X1/CLK
A1–A4
RWN
CSN
D0–D7
DTACKN
t
CSC
t
AS
t
RWS
t
DF
t
DAT
t
DAH
t
RWH
t
CSW
t
DD
NOT
VALID
t
CSD
t
DAL
t
DCR
t
AH
DATA VALID
t
DA
NOTE:
DACKN low requires two rising edges of X1 clock after CSN is low.
SD00147
Figure 4. Bus Timing (Read Cycle)
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