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參數(shù)資料
| 型號： | SCC68692E1F40 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Dual asynchronous receiver/transmitter DUART |
| 中文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CDIP40 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大?。?/td> | 193K |
| 代理商： | SCC68692E1F40 |
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Philips Semiconductors
Product specification
SCC68692
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
17
The bit definitions for this register are identical to the bit definitions
for CRA, with the exception of commands “Ex” and “Fx” which are
used for power down mode. These two commands are not used in
CRB. All other control actions that apply to CRA also apply to CRB.
SRA – Channel A Status Register
SRA[7] – Channel A Received Break
This bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received: further entries to the
FIFO are inhibited until the RxDA line to the marking state for at
least one-half a bit time two successive edges of the internal or
external 1X clock.
This will usually require a high time of one X1
clock period or 3 X1 edges since the clock of the controller is
not synchronous to the X1 clock.
When this bit is set, the Channel A ‘change in break’ bit in the ISR
(ISR[2]) is set. ISR[2] is also set when the end of the break
condition, as defined above, is detected.
The break detect circuitry can detect breaks that originate in the
middle of a received character. However, if a break begins in the
middle of a character, it must persist until at least the end of the next
character time in order for it to be detected.
SRA[6] – Channel A Framing Error
This bit, when set, indicates that a stop bit was not detected when
the corresponding data character in the FIFO was received. The
stop bit check is made in the middle of the first stop bit position.
SRA[5] – Channel A Parity Error
This bit is set when the ‘with parity’ or ‘force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity. In the special multidrop mode, the
parity error bit stores the received A/D bit.
SRA[4] – Channel A Overrun Error
This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new
character when the FIFO is full and a character is already in the
receive shift register waiting for an empty FIFO position. When this
occurs, the character in the receive shift register (and its break
detect, parity error and framing error status, if any) is lost. This bit is
cleared by a ‘reset error status’ command.
SRA[3] – Channel A Transmitter Empty (TxEMTA)
This bit will be set when the transmitter underruns, i.e., both the
TxEMT and TxRDY bits are set. This bit and TxRDY are set when
the transmitter is first enabled and at any time it is re-enabled after
either (a) reset, or (b) the transmitter has assumed the disabled
state. It is always set after transmission of the last stop bit of a
character if no character is in the THR awaiting transmission.
It is reset when the THR is loaded by the CPU, a pending
transmitter disable is executed, the transmitter is reset, or the
transmitter is disabled while in the underrun condition.
SRA[2] – Channel A Transmitter Ready (TxRDYA)
This bit, when set, indicates that the THR is empty and ready to be
loaded with a character. This bit is cleared when the THR is loaded
by the CPU and is set when the character is transferred to the
transmit shift register. TxRDY is reset when the transmitter is
disabled and is set when the transmitter is first enabled, e.g.,
characters loaded into the THR while the transmitter is disabled will
not be transmitted.
SRA[1] – Channel A FIFO Full (FFULLA)
This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the RHR. If a character is waiting in the
receive shift register because the FIFO is full, FFULL will not be
reset when the CPU reads the RHR.
SRA[0] – Channel A Receiver Ready (RxRDYA)
This bit indicates that a character has been received and is waiting
in the FIFO to be read by the CPU. It is set when the character is
transferred from the receive shift to the FIFO and reset when the
CPU reads the RHR, if after this read there are not more characters
still in the FIFO.
SRB – Channel B Status Register
The bit definitions for this register are identical to the bit definitions
for SRA, except that all status applies to the Channel B receiver and
transmitter and the corresponding inputs and outputs.
OPCR – Output Port Configuration Register
OPCR[7] – OP7 Output Select
This bit programs the OP7 output to provide one of the following:
0
The complement of OPR[7].
1
The Channel B transmitter interrupt output which is the
complement of TxRDYB. When in this mode OP7 acts as an
open-drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[6] – OP6 Output Select
This bit programs the OP6 output to provide one of the following:
0
The complement of OPR[6].
1
The Channel A transmitter interrupt output which is the
complement of TxRDYA. When in this mode OP6 acts as an
open-drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[5] – OP5 Output Select
This bit programs the OP5 output to provide one of the following:
0
The complement of OPR[5].
1
The Channel B transmitter interrupt output which is the
complement of ISR[5]. When in this mode OP5 acts as an
open-drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[4] – OP4 Output Select
This field programs the OP4 output to provide one of the following:
0
The complement of OPR[4].
1
The Channel A receiver interrupt output which is the complement
of ISR[1]. When in this mode OP4 acts as an open-drain output.
Note that this output is not masked by the contents of the IMR.
OPCR[3:2] – OP3 Output Select
This bit programs the OP3 output to provide one of the following:
00 The complement of OPR[3].
01 The counter/timer output, in which case OP3 acts as an
open-drain output. In the timer mode, this output is a square
wave at the programmed frequency. In the counter mode, the
output remains High until terminal count is reached, at which
time it goes Low. The output returns to the High state when the
counter is stopped by a stop counter command. Note that this
output is not masked by the contents of the IMR.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCC68692E1N40 | 功能描述:UART 接口集成電路 5V IND. UART 2 CH. MOT INTERF. RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SCC68692E1N40,602 | 功能描述:UART 接口集成電路 5V IND. UART 2 CH. RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SCC7600003 | 制造商:Denon Electronics 功能描述:GRILL ASS'YSCC76 |
| SCC76BK003 | 制造商:Denon 功能描述:GRILLE ASSY, DENON |
| SCC9521002-01B | 制造商:AIMTEC 制造商全稱:AIMTEC 功能描述:Rad. Tolerant 8-bit ROMless Microcontroller |
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