參數(shù)資料
型號： SCC68692E1F40
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Dual asynchronous receiver/transmitter DUART
中文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CDIP40
文件頁數(shù)： 7/30頁
文件大小： 193K
代理商： SCC68692E1F40
Philips Semiconductors
Product specification
SCC68692
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
7
AC CHARACTERISTICS
1, 2, 4
SYMBOL
FIGURE
PARAMETER
LIMITS
Typ
3
UNIT
Min
Max
Reset Timing
t
RES
Bus Timing5
t
AS
t
AH
t
RWS
t
RWH
t
CSW8
t
CSD9
t
DD
t
DA8
t
DF8
t
DI8
t
DS
t
DH
t
DAL
t
DCR
t
DCW
t
DAH
I
DAT
t
CSC7
Port Timing
5
t
PS
t
PH
t
PD
Interrupt Timing
t
IR10
1
RESET pulse width
200
ns
4,5,6
4,5,6
4,5,6
4,5,6
4,5,6
4,5,6
4,5,6
4
4,5,6
4
4,5,6
4,5,6
4,5,6
4,5,6
4,5,6
4,5,6
4,5,6
4,5,6
A1–A4 setup time to CSN Low
A1–A4 hold time from CSN Low
RWN setup time to CSN High
RWN holdup time to CSN High
CSN High pulse width
CSN or IACKN High from DTACKN Low
Data valid from CSN or IACKN Low
RDN Low to data bus active
Data bus floating from CSN or IACKN High
RDN High to data bus invalid
Data setup time to CLK High
Data hold time from CSN High
DTACKN Low from read data valid
DTACKN Low (read cycle) from CLK High
DTACKN Low (write cycle) form CLK High
DTACKN High from CSN or IACKN High
DTACKN High impedance from CSN or IACKN High
CSN or IACKN setup time to clock High
10
100
0
0
160
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
175
15
125
20
100
0
0
125
125
100
125
90
7
7
7
Port input setup time to CSN Low
Port input hold time from CSN High
Port output valid from CSN High
0
0
ns
ns
ns
400
6
INTRN (or OP3–OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (break interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
300
300
300
300
300
300
ns
ns
ns
ns
ns
ns
Clock Timing
t
CLK
f
CLK11
t
CTC
f
CTC9
t
RX
f
RX9
7
7
7
7
7
X1/CLK High or Low time
X1/CLK frequency
CTCLK (IP2) High or Low time
CTCLK (IP2) frequency
RxC High or Low time
RxC frequency (16X)
100
0
100
100
220
100
100
220
0
0
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
3.6864
4
4
7
(1X)
2
1
t
TX
f
TX9
7
TxC High or Low time
TxC frequency (16X)
7
(1X)
2
1
Transmitter Timing
t
TXD
t
TCS
Receiver Timing
t
RXS
t
RXH
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Typical values are at +25
°
C, typical supply voltages, and typical processing parameters.
8
8
TxD output delay from TxC external clock input on IP pin
Output delay from TxC low at OP pin to TxD data output
350
150
ns
ns
9
9
RxD data setup time before RxC high at external clock input on IP pin
RxD data hold time after RxC high at external clock input on IP pin
240
200
ns
ns
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