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參數(shù)資料
| 型號(hào)： | sda 9206 |
| 廠商： | SIEMENS AG |
| 英文描述： | ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器) |
| 中文描述： | 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 15/54頁(yè) |
| 文件大?。?/td> | 530K |
| 代理商： | SDA 9206 |
SDA 9206
Semiconductor Group
15
1999-02-10
2
System Description
2.1
A/D Converter for YUV Inputs
2.1.1
The SDA 9206 implements 3 independent 8-Bit A/D converters.
Maximum conversion rate is 30 MHz.
Introduction
2.1.2
The amplification of the input signals can be adjusted via
I
2
C Bus. An internal prefiltering
of the analog input signals is implemented. The typ. frequency response of the analog
antialiasing prefilter is shown in
figure 10
.
Input Signal Amplification, Prefiltering
Figure 10
Frequency Response of the Analog Antialiasing Prefilter
-20
-30
-40
10
-50
-10
dB
0
10
UED10458
Frequency
MHz
-70
0
1
2
10
-60
5
5
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