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參數(shù)資料
| 型號： | sda 9206 |
| 廠商： | SIEMENS AG |
| 英文描述： | ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時鐘發(fā)生器的A/D轉換器) |
| 中文描述： | 在抗混疊濾波器和時鐘產(chǎn)生單元內(nèi)置模數(shù)轉換器（帶有片內(nèi)去混疊和時鐘發(fā)生器的的A / D轉換器） |
| 文件頁數(shù)： | 23/54頁 |
| 文件大?。?/td> | 530K |
| 代理商： | SDA 9206 |
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SDA 9206
Semiconductor Group
23
1999-02-10
During 1fh mode (2FH = 0) the digital HPLL also supplies a noise-suppressed vertical
pulse obtained by digital integration of the main equalizing pulses. An integration time of
26.6
μ
s or 11.3
μ
s can be set by the
I
2
C Bus. This functionality is switched off during 2fh
mode (2FH = 1).
2.3.2
Vertical sync processing consists of:
625/525 line detection
vertical noise suppression
The vertical pulses are obtained from the SYNC signal by integration. The 625/525 line
detector measures the number of lines per field. By taking the average of the individual
measurements with two up/down counters, the status bits ’FF’ ad ’FFGF’ are obtained.
When vertical noise suppression is switched on (VOFF = 0), the vertical pulse obtained
from the SYNC signal by integration is admitted only within a preset window (refer to
timing diagram) and appears as a VS pulse. The width of the window can be set via the
I
2
C Bus.
In the temporary absence of vertical pulses in SYNC, a continuous VS can be generated
by switching on a ’flywheel mode’ (SCHW = 1) providing a number of lines per field of
312.5 or 262.5 respectively.
When interference to SYNC is heavy, missing vertical pulses can be supplemented by
switching on the flywheel mode and vertical interference can be eliminated by switching
on the noise suppression circuitry. Noise suppression and the flywheel mode can be
enabled independently of each other.
There is also the possibility of generating VS in the free-running mode. The VS pulses
are then completely independent of the vertical sync pulse in SYNC. When FREE = 1
and SCHW = 1, a VS pulse is generated every 262.5 or 312.5 lines (VF = 1 or 0
respectively). When FREE = 1 and SCHW = 0, a VS pulse is generated every 279 or 339
lines (VF = 1 or 0 respectively). Free-running generation of VS occurs every 262 or 312
in the terminal mode (TERM = 1).
Vertical Sync Processing (only available for 1fh mode)
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