參數(shù)資料
型號(hào)： sda 9206
廠商： SIEMENS AG
英文描述： ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器)
中文描述： 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器）
文件頁(yè)數(shù)： 49/54頁(yè)
文件大?。?/td> 530K
代理商： SDA 9206
SDA 9206
Semiconductor Group
49
1999-02-10
3.2
Characteristics (Assuming Recommended Operating Conditions)
(cont’d)
Parameter
Symbol
Limit Values
nom.
Unit
Remark
min.
26
26
10
10
- 2
25
max.
Low time 13.5 MHz
High time 13.5 MHz
Low time 27 MHz
High time 27 MHz
Skew
Frequency range
when PLL is locked at
SYNC input signal
Performance of A/D Conversion (8-Bit)
Test Conditions: ADC Clock = 27 MHz, DATDEL = 000, xAMP = 0000, VIPP = 2 Vpp
Sampling rate
27
Differential linearity
(DC)
Integral linearity (DC) INLE
Clamping level
accuracy
Gain error (DC)
GE
Gain matching error
(DC)
Differential gain
DG
Differential phase
DP
Signal to noise ratio
at 4.4 MHz sinus
t
WL13
t
WH13
t
WL27
t
WH27
t
SK
f
ns
ns
ns
ns
ns
MHz
13.5 MHz
13.5 MHz
27 MHz
27 MHz
C
L,CLK1
=
C
L,CLK2
± 4.8% at 27 MHz
S1CL = 11, S2CL = 11
0
27
2
35
MHz
LSB
DNLE
± 0.5
± 1
± 3
LSB
LSB
CLA
0.5
± 6
± 3
LSB
LSB
GME
3
3
%
deg
dB
Not tested
Not tested
Without harmonics
α
S/N
45
48
Harmonic Distortion
2./4. order
3. order
5./6. order
- 42
- 42
- 48
dB
dB
dB
4.4 MHz fundamental
4.4 MHz fundamental
4.4 MHz fundamental
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