參數(shù)資料
型號(hào)： sda 9206
廠商： SIEMENS AG
英文描述： ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器)
中文描述： 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器）
文件頁數(shù)： 30/54頁
文件大?。?/td> 530K
代理商： SDA 9206
SDA 9206
Semiconductor Group
30
1999-02-10
Subaddress 01
H
Bit
D7...D4
Subaddress 02
H
Bit
D7
Name
YD
Function
Delay compensation in Y-signal path (13.5 MHz clocks):
0000:
... - 0.30
μ
s
0001
0010
0011
0100:
... 0
μ
s
:
:
1110
1111:
... 0.81
μ
s
Reserved
D3...D0
0000
Name
I2
Function
Voltage level of H2I2 output (SELH2I2 = 1):
0:
Low voltage at pin H2I2
1:
High voltage at pin H2I2
Voltage level of H1I1 output (SELH1I1 = 1):
0:
Low voltage at pin H1I1
1:
High voltage at pin H1I1
Function of pin H2I2:
0:
H2 (line frequency, start and stop programmable)
1:
I2 (low/high programmable)
Function of pin H1I1:
0:
H1 (line frequency, start and stop programmable)
1:
I1 (low/high programmable)
Reserved
Reserved
Reserved
Reserved
D6
I1
D5
SELH2I2
D4
SELH1I1
D3
D2
D1
D0
0
0
0
0
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