參數(shù)資料
型號(hào)： sda 9206
廠商： SIEMENS AG
英文描述： ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器)
中文描述： 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器）
文件頁(yè)數(shù)： 47/54頁(yè)
文件大?。?/td> 530K
代理商： SDA 9206
SDA 9206
Semiconductor Group
47
1999-02-10
3.2
Characteristics (Assuming Recommended Operating Conditions)
Parameter
Symbol
Limit Values
nom.
Unit
Remark
min.
max.
Supply Currents
Analog supply current
I
ADD
Digital supply current
I
DD
120
40
mA
mA
Sum of all
V
ADDx
pins
Sum of all
V
DD
pins +
V
DDDTO
Sum of all V
DDQ
pins
Output stage supply
current
Reference Inputs for Analog Inputs AINY, AINU, AINV
Reference ladder
resistance
I
DDQ
40
mA
R
REF
175
250
325
For each converter
between REFH and
REFL
Reference Inputs for Analog Input SYNC
Reference ladder
resistance
R
REF
280
400
520
For each converter
between REFH and
REFL
All TTL Inputs
Input current
- 300
300
μ
A
V
I
= 0 V...
V
DDQ
Note:
internal pullup/
pulldown-circuits
I
2
C Input/Output SDA
L-output voltage
Analog Inputs
Analog input leakage
current
Analog input
capacitance
TTL Outputs Port A, Port B, VS, HS, BLN, H1, H2, RESOUTN (
V
DDQ
= 3.3 V or 5 V)
L-output voltage
V
QL
0
H-output voltage
V
QH
2.4 V
High impedance state
output current
V
QL
0.6
V
I
= 4 mA
I
AIN
- 100
100
nA
AINY, AINU, AINV,
SYNC each
AINY, AINU, AINV,
SYNC each
C
I
10
pF
0.4
V
DDQ
20
V
1
μ
A
I
= 1 mA
I
= - 0.5 mA
V
Q
= 0 V...
V
DDQ
Port A, Port B, VS,
HS, BLN
I
QZ
- 20
Load capacitance
C
L
25
pF
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