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參數(shù)資料
| 型號(hào)： | SI5310-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 13/26頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR SI5310 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 已用 IC / 零件： | SI5310 |
| 已供物品： | 板 |
| 其它名稱： | 336-1140 |
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Si5310
20
Rev. 1.3
12, 13
CLKOUT–,
CLKOUT+
OCML
Differential Clock Output.
The clock output signal is a regenerated version of
the input clock signal present on CLKIN. It is phase
aligned with MULTOUT and is updated on the rising
edge of MULTOUT.
Note: Connection of an improperly terminated
transmission line to the CLKOUT output can cause
reflections that may adversely affect the
performance of the MULTOUT output. If the
CLKOUT output is not used, these pins should be
either tied to VDD (recommended), left
unconnected, or connected to a properly
terminated transmission line.
15
PWRDN/CAL
I
LVTTL
Power Down.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a high-to-
low transition on this pin. (See "4.9. PLL Self-Cali-
Note: This input has a weak internal pulldown.
16, 17
MULTOUT–,
MULTOUT+
OCML
Differential Multiplier Output.
The multiplier output is generated from the signal
present on CLKIN. In the absence of CLKIN, the
REFCLK is used to bound the frequency of MUL-
TOUT according to Table 4 on page 8.
Note: Connection of an improperly terminated
transmission line to the MULTOUT output can
cause reflections that may adversely affect the
CLKOUT output. If the MULTOUT output is not
used, these pins should be either tied to VDD
(recommended), left unconnected, or connected to
a properly terminated transmission line.
19
MULTSEL
I
LVTTL
Multiplier Rate Select.
This pin configures the onboard PLL-based clock
multiplier for clock generation at one of two user
selectable clock rates.
Note: This input has a weak internal pulldown.
20
NC
No Connect.
Table 11. Si5310 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5310-GM | 功能描述:鎖相環(huán) - PLL Clock Multiplier Regenerator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SI5310-GMR | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5311 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC |
| SI53112-A00AGM | 功能描述:IC BUFFER ZDB PCIE 1:12 64-QFN 制造商:silicon labs 系列:- 包裝:托盤(pán) 零件狀態(tài):有效 PLL:是 主要用途:Intel QPI，PCI Express（PCIe） 輸入:時(shí)鐘 輸出:HCSL 電路數(shù):1 比率 - 輸入:輸出:1：12 差分 - 輸入:輸出:是/是 頻率 - 最大值:133.33MHz 電壓 - 電源:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-VFQFN 裸露焊盤(pán) 供應(yīng)商器件封裝:64-QFN（9x9） 標(biāo)準(zhǔn)包裝:260 |
| SI53112-EK | 功能描述:Si53112 - Timing, Clock Buffer Evaluation Board 制造商:silicon labs 系列:- 零件狀態(tài):有效 主要用途:計(jì)時(shí)，時(shí)鐘緩沖器 嵌入式:- 使用的 IC/零件:Si53112 主要屬性:- 輔助屬性:- 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
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