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| 型號： | SI5310-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR SI5310 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時，時鐘發(fā)生器 |
| 已用 IC / 零件： | SI5310 |
| 已供物品： | 板 |
| 其它名稱： | 336-1140 |
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Si5310
14
Rev. 1.3
4.1. DSPLL
The PLL structure (shown in Figure 1 on page 5) utilizes
Silicon Laboratories' DSPLL technology to produce
superior jitter performance while eliminating the need
for external loop filter components found in traditional
PLL implementations. This is achieved by using a digital
signal processing (DSP) algorithm to replace the loop
filter commonly found in analog PLL designs. This
algorithm processes the phase detector error term and
generates a digital control value to adjust the frequency
of
the
voltage-controlled
oscillator
(VCO).
The
technology produces clocks with less jitter than is
generated using traditional methods. In addition,
because external loop filter components are not
required, sensitive noise entry points are eliminated,
thus making the DSPLL less susceptible to board-level
noise sources.
4.2. Clock Multiplier
The DSPLL phase locks to the clock input signal
(CLKIN) and generates an output clock (MULTOUT) at
a multiple of the input clock frequency. The MULTOUT
output is configured to operate in either the 150–
167 MHz frequency range or in the 600–668 MHz
frequency range using the MULTSEL control input as
indicated in Table 9. Values for typical applications are
given in Table 10.
The amount of jitter present in the MULTOUT output is a
function of the DSPLL jitter transfer function and jitter
generation characteristic. Details are provided in the
PLL Performance section of this document. (See
can tolerate on the CLKIN input is specified in Tables 5
and 6.
The DSPLL implementation in the Si5310 is insensitive
to the duty cycle of the CLKIN input. The MULTOUT
output will continue to exhibit a very good duty cycle
characteristic even when the CLKIN input duty cycle is
degraded.
4.3. 1x Multiplication
The Si5310 Clock Multiplier function may also be
utilized as a 1x multiplier in order to provide jitter
attenuation
and
duty
cycle
correction
without
multiplication of the input clock frequency.
Note: When the Si5310 is configured as a 1:1 multiplier, the
CLKOUT output is not valid.
4.4. Clock Regeneration
The DSPLL is used to regenerate a jitter-attenuated
version of the CLKIN input, resulting in a “clean”
CLKOUT output with sharp rising and falling edges. The
CLKOUT output is a resampled version of the CLKIN
input
with
all
CLKOUT
transitions
occurring
synchronously with the rising edges of the MULTOUT
output. The rising edges of CLKOUT are insensitive to
the location of the falling edges of the CLKIN input.
Thus the period of CLKOUT, measured rising edge to
rising edge, is not affected by the CLKIN duty cycle or
by jitter on the falling edge of CLKIN.
The falling edges of CLKOUT may be affected by the
location of the CLKIN falling edges as follows: If the
duty cycle error of CLKIN is significant relative to the
period of MULTOUT, then
1. The CLKOUT duty cycle may deviate from 50% (the falling
edge of CLKOUT will be time quantized to the nearest
rising edge of MULTOUT.)
2. Jitter on the falling edges of CLKIN may result in a
CLKOUT duty cycle that alternates between two discrete
values.
Note: When the Si5310 is configured as a 1:1 multiplier, the
CLKOUT output is not valid.
4.5. Reference Clock
The Si5310 CMU requires an external reference clock
applied to the REFCLK input for normal device
operation. When REFCLK is absent, the LOL alarm will
always be asserted when it has been determined that
no activity exists on REFCLK, indicating the lock status
of the PLL is unknown. Additionally, the reference clock
input is used to center the DSPLL and also to act as a
reference for determination of the PLL lock status.
REFCLK is a multiple of the CLKIN frequency, and can
be provided in any one of five frequency ranges (9.375–
10.438 MHz, 18.78–20.875 MHz, 37.500–41.750 MHz,
75.00–83.50 MHz, or 150–167.00 MHz). The REFCLK
rate is automatically detected by the Si5310, so no
control inputs are needed for REFCLK frequency
selection. The REFCLK input may be synchronous or
asynchronous with respect to the CLKIN input. The
frequency relationship between REFCLK and CLKIN is
indicated in Table 9. In many applications, it may be
desirable to tie REFCLK and CLKIN together and drive
them from the same clock source. The Si5310 is
insensitive to the phase relationship between CLKIN
and REFCLK, so these differential inputs may be driven
in phase or 180° out of phase if this simplifies board
layout. Values for typical applications are given in
4.6. DSPLL Lock Detection (Loss-of-Lock)
The Si5310 provides lock-detect circuitry that indicates
whether the DSPLL has achieved frequency lock with
the incoming CLKIN signal. The circuit compares the
frequency of a divided down version of the multiplier
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5310-GM | 功能描述:鎖相環(huán) - PLL Clock Multiplier Regenerator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SI5310-GMR | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5311 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC |
| SI53112-A00AGM | 功能描述:IC BUFFER ZDB PCIE 1:12 64-QFN 制造商:silicon labs 系列:- 包裝:托盤 零件狀態(tài):有效 PLL:是 主要用途:Intel QPI，PCI Express（PCIe） 輸入:時鐘 輸出:HCSL 電路數(shù):1 比率 - 輸入:輸出:1：12 差分 - 輸入:輸出:是/是 頻率 - 最大值:133.33MHz 電壓 - 電源:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-VFQFN 裸露焊盤 供應(yīng)商器件封裝:64-QFN（9x9） 標(biāo)準(zhǔn)包裝:260 |
| SI53112-EK | 功能描述:Si53112 - Timing, Clock Buffer Evaluation Board 制造商:silicon labs 系列:- 零件狀態(tài):有效 主要用途:計(jì)時，時鐘緩沖器 嵌入式:- 使用的 IC/零件:Si53112 主要屬性:- 輔助屬性:- 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
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