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參數(shù)資料
型號(hào): SI5310-EVB
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 25/26頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR SI5310
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
已用 IC / 零件: SI5310
已供物品:
其它名稱: 336-1140
Si5310
8
Rev. 1.3
Table 4. AC Characteristics (PLL Performance Characteristics)
(VDD = 2.5 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Tolerance
(MULTSEL = 0,
MULTOUT = 600 to 668 MHz)
JTOL(PP)
Jitter Tolerance
(MULTSEL = 1,
MULTOUT = 150 to 167 MHz)
JTOL(PP)
Jitter Generation (MULTOUT, CLKOUT)
(MULTSEL = 0,
MULTOUT = 600 to 668 MHz)*
(measurement BW = 12kHz to 1MHz)
JGEN(rms) Clock Input (MHz) =
37.500 to 41.750
—2.5
5.4
psrms
Clock Input (MHz) =
75.000 to 83.500
—1.6
3.1
psrms
Clock Input (MHz) =
150.000 to 167.000
—0.9
1.6
psrms
Clock Input (MHz) =
300.000 to 334.000
—0.6
1.3
psrms
Clock Input (MHz) =
600.000 to 668.000
—0.4
0.8
psrms
Jitter Generation (MULTOUT, CLKOUT)
(MULTSEL = 1,
MULTOUT = 150 to 167 MHz)*
(measurement BW = 12kHz to 1MHz)
JGEN(rms) Clock Input (MHz) =
9.375 to 10.438
—8.5
34.0
psrms
Clock Input (MHz) =
18.750 to 20.875
—5.0
19.7
psrms
Clock Input (MHz) =
37.500 to 41.750
—3.7
15.2
psrms
Clock Input (MHz) =
75.000 to 83.500
—2.3
15.2
psrms
Clock Input (MHz) =
150.000 to 167.000
—1.1
3.0
psrms
Jitter Transfer Bandwidth
(MULTSEL = 0,
MULTOUT = 600 to 668 MHz)*
JBW
Clock Input (MHz) =
37.500 to 41.750
75
105
kHz
Clock Input (MHz) =
75.000 to 83.500
150
210
kHz
Clock Input (MHz) =
150.000 to 167.000
300
420
kHz
Clock Input (MHz) =
300.000 to 334.000
600
840
kHz
Clock Input (MHz) =
600.000 to 668.000
1200
1680
kHz
*Note: See PLL Performance section of this document for test descriptions.
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