參數(shù)資料
型號: SI5322/23-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 14/24頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR SI5322/23
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
已用 IC / 零件: SI5322,SI5323
已供物品: 板,線纜,CD,文檔
Si5322
Rev. 0.51
21
Table 11. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
0.50 BSC.
E
5.42 REF.
D
5.42 REF.
E2
4.00
4.20
D2
4.00
4.20
GE
4.53
GD
4.53
X
0.28
Y
0.89 REF.
ZE
6.31
ZD
6.31
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
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參數(shù)描述
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