VID fCKIN <" />
參數(shù)資料
型號: SI5322/23-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 20/24頁
文件大小: 0K
描述: BOARD EVAL FOR SI5322/23
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
已用 IC / 零件: SI5322,SI5323
已供物品: 板,線纜,CD,文檔
Si5322
Rev. 0.51
5
Differential Input
Voltage Swing
VID
fCKIN < 212.5 MHz
0.2
VPP
fCKIN > 212.5 MHz
0.25
VPP
Output Clocks (CKOUTn)1
Common Mode
CKOVCM
LVPECL 100
load
line-to-line
VDD
1.42
—VDD
1.25
V
Differential Output Swing
CKOVD
LVPECL 100
load
line-to-line
1.1
1.9
VPP
Single-ended Output Swing
CKOVSE
LVPECL 100
load
line-to-line
0.5
0.93
VPP
Differential Output Voltage
CKOVD
CML 100
load
line-to-line
350
425
500
mVPP
Common Mode
Output Voltage
CKOVCM
CML 100
load
line-to-line
—VDD
0.36
—V
Differential
Output Voltage
CKOVD
LVDS 100
load
line-to-line
500
700
900
mVPP
Low swing LVDS 100
load
line-to-line
350
425
500
mVPP
Common Mode
Output Voltage
CKOVCM
LVDS 100
load
line-to-line
1.125
1.2
1.275
V
Differential Output
Resistance
CKORD
CML, LVDS, LVPECL
200
Output Voltage Low
CKOVOLLH
CMOS
0.4
V
Output Voltage High
CKOVOHLH
VDD =1.71V
CMOS
0.8 x VDD
——
V
Output Drive Current
CKOIO
CMOS
Driving into CKOVOL for out-
put low or CKOVOH for output
high. CKOUT+ and CKOUT–
shorted externally.
7.5
32
mA
VDD =1.8 V
VDD =3.3 V
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. LVPECL outputs require nominal VDD > 2.5 V.
2. No overshoot or undershoot.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
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