Si5322
Rev. 0.51
23
DOCUMENT CHANGE LIST
Revision 0.44 to Revision 0.45
Condensed format.
Revision 0.45 to Revision 0.46
Removed references to latency control, INC, and
DEC in figures and text.
Changed LVTTL to LVCMOS in Table 2, “Absolute
Maximum Ratings,” on page 5.
Added Figure 1, “Typical Phase Noise Plot,” on page
4.
Revision 0.46 to Revision 0.47
Removed Figure 1. “Typical Phase Noise Plot.”
Changed pins 11 and 15 from NC to VDD in “3. Pin Revision 0.47 to Revision 0.5
Changed 1.8 V operating range to ±5%.
Updated Table 1 on page 4.
Updated Table 2 on page 5.
down resistors for 3-level inputs.
Updated SFOUT values.
Revision 0.5 to Revision 0.51
Changed “any-rate” to “any-frequency” throughout.
Expanded spec tables 1 through 7.
Added clarification that CMOS output format is not
available in PLL bypass mode.