參數(shù)資料
型號: SI5322/23-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 6/24頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR SI5322/23
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
已用 IC / 零件: SI5322,SI5323
已供物品: 板,線纜,CD,文檔
Si5322
14
Rev. 0.51
3. Pin Descriptions: Si5322
Table 9. Si5322 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
1RST
ILVCMOS
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state. Clock out-
puts are tristated during reset. After rising edge of RST sig-
nal, the Si5322 will perform an internal self-calibration.
This pin has a weak pull-up.
2
FRQTBL
I
3-Level
Frequency Table Select.
Selects SONET/SDH, datacom, or SONET/SDH to datacom
frequency table.
L = SONET/SDH.
M=Datacom.
H = SONET/SDH to Datacom.
The pin has a weak pull-up and weak pull-down and
defaults to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
3C1B
O
LVCMOS
CKIN1 Loss of Signal.
Active high loss-of-signal indicator for CKIN1. Once trig-
gered, the alarm will remain active until CKIN1 is validated.
0 = CKIN1 present.
1 = LOS on CKIN1.
4C2B
O
LVCMOS
CKIN2 Loss of Signal.
Active high loss-of-signal indicator for CKIN2. Once trig-
gered, the alarm will remain active until CKIN2 is validated.
0 = CKIN2 present.
1 = LOS on CKIN2.
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
FRQTBL
AUTOSEL
RST
C2B
C1B
GND
VDD
GND
VDD
CK
IN
2+
CK
IN2–
D
BL2_
BY
VDD
CK
IN
1+
CK
IN1–
CS_CA
BWSEL0
BWSEL1
FRQSEL1
FRQSEL2
FRQSEL3
CKO
UT
1
SF
O
UT1
GN
D
VDD
SF
OU
T0
CK
OU
T2
CK
OU
T2
+
NC
GND
Pad
FRQSEL0
GND
9
18
19
28
NC
GND
CK
OU
T
1
+
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