參數(shù)資料
型號: SI5351B-A-GT
廠商: Silicon Laboratories Inc
文件頁數(shù): 18/72頁
文件大?。?/td> 0K
描述: IC CLK GEN PLL BLANK CUST 10MSOP
標(biāo)準(zhǔn)包裝: 50
系列: MultiSynth™
類型: *
PLL:
輸入: 晶體
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:8
差分 - 輸入:輸出: 無/無
頻率 - 最大: 133MHz
除法器/乘法器: 是/無
電源電壓: 2.25 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
Si5351A/B/C
Preliminary Rev. 0.95
25
8. Register Descriptions
Reset value = 0000 0000
Register 0. Device Status
Bit
D7D6D5D4D3D2D1D0
Name
SYS_INIT
LOL_B
LOL_A
LOS
REVID[1:0]
Type
RRRRR
R
Bit
Name
Function
7SYS_INIT
System Initialization Status.
During power up the device copies the content of the NVM into RAM and performs a system
initialization. The device is not operational until initialization is complete. It is not recom-
mended to read or write registers in RAM through the I2C interface until initialization is com-
plete. An interrupt will be triggered (INTR pin = 0, Si5351C only) during the system
initialization period.
0: System initialization is complete. Device is ready.
1: Device is in system initialization mode.
6LOL_B
PLLB Loss Of Lock Status.
Si5351A/C only. PLLB will operate in a locked state when it has a valid reference from CLKIN
or XTAL. A loss of lock will occur if the frequency of the reference clock forces the PLL to
operate outside of its lock range as specified in Table 3, or if the reference clock fails to meet
the minimum requirements of a valid input signal as specified in Table 4. An interrupt will be
triggered (INTR pin = 0, Si5351C) during a LOL condition.
0: PLL B is locked.
1: PLL B is unlocked. When the device is in this state it will trigger an interrupt causing the
INTR pin to go low (Si5351C only).
5LOL_A
PLL A Loss Of Lock Status.
PLL A will operate in a locked state when it has a valid reference from CLKIN or XTAL. A loss
of lock will occur if the frequency of the reference clock forces the PLL to operate outside of
its lock range as specified in Table 3, or if the reference clock fails to meet the minimum
requirements of a valid input signal as specified in Table 4. An interrupt will be triggered
(INTR pin = 0, Si5351C only) during a LOL condition.
0: PLL A is operating normally.
1: PLL A is unlocked. When the device is in this state it will trigger an interrupt causing the
INTR pin to go low (Si5351C only).
4LOS
CLKIN Loss Of Signal (Si5351C Only).
A loss of signal status indicates if the reference clock fails to meet the minimum requirements
of a valid input signal as specified in Table 4. An interrupt will be triggered (INTR pin = 0,
Si5351C only) during a LOS condition.
0: Valid clock signal at the CLKIN pin.
1: Loss of signal detected at the CLKIN pin.
3:2
Reserved
Leave as default.
1:0
REVID[1:0] Revision ID. Device revision number. Set at the factory.
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SI5351B-B01556-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Trays