Si5351A/B/C
6
Preliminary Rev. 0.95
Table 5. Output Clock Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA =–40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Frequency Range
FCLK
0.008
—
160
MHz
Load Capacitance
CL
—5
15
pF
Duty Cycle
DC
Measured at VDD/2,
fCLK =50MHz
45
50
55
%
Rise/Fall Time
tr
20%–80%, CL =5pF,
Drive Strength = 8 mA
0.5
1
1.5
ns
tf
0.5
1
1.5
ns
Output High Voltage
VOH
CL =5pF
VDD – 0.6
—
V
Output Low Voltage
VOL
——
0.6
V
Period Jitter
JPER
Measured over 10k cycles
—
35
100
ps pk-pk
Period Jitter VCXO
JPER_VCXO
—
60
110
ps pk-pk
Cycle-to-Cycle Jitter
JCC
Measured over 10k cycles
—30
90
ps pk
Cycle-to-Cycle Jitter
VCXO
JCC_VCXO
—50
95
ps pk
RMS Phase Jitter
JRMS
12 kHz–20 MHz
—
3.5
11
ps rms
RMS Phase Jitter VCXO JRMS_VCXO
—
8.5
18.5
ps rms
Table 6. Crystal Requirements1,2 Parameter
Symbol
Min
Typ
Max
Unit
Crystal Frequency
fXTAL
25
—
27
MHz
Load Capacitance
CL
6—
12
pF
Equivalent Series Resistance
rESR
——
150
Crystal Max Drive Level
dL
——
100
W
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitors in addition to external 2 pF load capacitors.
2. Refer to “AN551: Crystal Selection Guide” for more details.