參數(shù)資料
型號: SI5367/68-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 22/80頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR SI5367/68
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
已用 IC / 零件: SI5367,SI5368
已供物品: 板,線纜,CD,文檔
Si5367
Rev. 0.5
29
Reset value = 0000 0000
Register 10.
Bit
D7
D6
D5
D4
D3D2D1D0
Name
DSBL5_REG
DSBL4_REG DSBL3_REG DSBL2_REG DSBL1_REG
Type
RR
R/W
R
R/W
R
Bit
Name
Function
7:6
Reserved
5
DSBL5_REG DSBL5_REG.
This bit controls the powerdown and disable of the CKOUT5 output buffer. If disable
mode is selected, the NC5_LS output divider is also powered down.
0: CKOUT5 enabled.
1: CKOUT5 disabled.
4
Reserved
3
DSBL4_REG DSBL4_REG.
This bit controls the powerdown and disable of the CKOUT4 output buffer. If disable
mode is selected, the NC4 output divider is also powered down.
0 = CKOUT4 enabled
1 = CKOUT4 disabled
2
DSBL3_REG DSBL3_REG.
This bit controls the powerdown and disable of the CKOUT3 output buffer. If disable
mode is selected, the NC3 output divider is also powered down.
0: CKOUT3 enabled
1: CKOUT3 disabled
1
DSBL2_REG DSBL2_REG.
This bit controls the powerdown and disable of the CKOUT2 output buffer. If disable
mode is selected, the NC2 output divider is also powered down.
0: CKOUT2 enabled
1: CKOUT2 disabled
0
DSBL1_REG DSBL1_REG.
This bit controls the powerdown and disable of the CKOUT1 output buffer. If disable
mode is selected, the NC1 output divider is also powered down.
0: CKOUT1 enabled
1: CKOUT1 disabled
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