參數資料
型號: SI5367/68-EVB
廠商: Silicon Laboratories Inc
文件頁數: 65/80頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR SI5367/68
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
已用 IC / 零件: SI5367,SI5368
已供物品: 板,線纜,CD,文檔
Si5367
68
Rev. 0.5
Table 11. Si5367 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
1, 2, 4, 17, 20,
22, 23, 24, 25,
37, 47, 48, 49,
50, 51, 52, 53,
56, 66, 67, 72,
73, 74, 75, 80,
85, 95
NC
No Connect.
These pins must be left unconnected for normal opera-
tion.
3RST
ILVCMOS
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state and
forces the device registers to their default value. Clock
outputs are disabled during reset. The part must be pro-
grammed after a reset or power-on to get a clock output.
See Family Reference Manual for details.
This pin has a weak pull-up.
5, 6, 15, 27, 32,
42, 62, 63, 76,
79, 81, 84, 86,
89, 91, 94, 96,
99, 100
VDD
Vdd
Supply
VDD.
The device operates from a 1.8 or 2.5 V supply. Bypass
capacitors should be associated with the following VDD
pins:
Pins
Bypass Cap
5, 6
0.1 F
15
0.1 F
27
0.1 F
62, 63
0.1 F
76, 79
1.0 F
81, 84
0.1 F
86, 89
0.1 F
91, 94
0.1 F
96, 99, 100
0.1 F
7, 8, 14, 16, 18,
19, 21, 26, 28,
31, 33, 36, 38,
41, 43, 46, 54,
55, 64, 65
GND
Supply
Ground.
This pin must be connected to system ground. Minimize
the ground path impedance for optimal performance.
9C1B
O
LVCMOS
CKIN1 Invalid Indicator.
This pin performs the CK1_BAD function if
CK1_BAD_PIN = 1 and is tristated if CK1_BAD_PIN =0.
Active polarity is controlled by CK_BAD_POL.
0 = No alarm on CKIN1.
1 = Alarm on CKIN1.
10
C2B
O
LVCMOS
CKIN2 Invalid Indicator.
This pin performs the CK2_BAD function if
CK2_BAD_PIN = 1 and is tristated if CK2_BAD_PIN =0.
Active polarity is controlled by CK_BAD_POL.
0 = No alarm on CKIN2.
1 = Alarm on CKIN2.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
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