CKOVCM LVPECL 100 load line-to-line V
參數(shù)資料
型號(hào): SI5367/68-EVB
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 56/80頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR SI5367/68
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
已用 IC / 零件: SI5367,SI5368
已供物品: 板,線纜,CD,文檔
Si5367
6
Rev. 0.5
Common Mode
CKOVCM
LVPECL 100
load
line-to-line
VDD –1.42
VDD –1.25
V
Differential Output
Swing
CKOVD
LVPECL 100
load line-
to-line
1.1
1.9
VPP
Single Ended Output
Swing
CKOVSE
LVPECL 100
load line-
to-line
0.5
0.93
VPP
Differential Output
Voltage
CKOVD
CML 100
load line-to-
line
350
425
500
mVPP
Common Mode Output
Voltage
CKOVCM
CML 100
load line-to-
line
—VDD–0.36
V
Differential Output
Voltage
CKOVD
LVDS
100
load line-to-line
500
700
900
mVPP
Low Swing LVDS
100
load line-to-line
350
425
500
mVPP
Common Mode Output
Voltage
CKOVCM
LVDS 100
load line-to-
line
1.125
1.2
1.275
V
Differential Output
Resistance
CKORD
CML, LVPECL, LVDS
200
Output Voltage Low
CKOVOLLH
CMOS
0.4
V
Output Voltage High
CKOVOHLH
VDD =1.71V
CMOS
0.8 x VDD
——
V
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Current draw is independent of supply voltage.
2. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
3. No under- or overshoot is allowed.
4. LVPECL outputs require nominal VDD
≥ 2.5 V.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference
Manual for more details.
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