參數(shù)資料
型號: SI5367/68-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 9/80頁
文件大小: 0K
描述: BOARD EVAL FOR SI5367/68
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
已用 IC / 零件: SI5367,SI5368
已供物品: 板,線纜,CD,文檔
Si5367
Rev. 0.5
17
3. Functional Description
The Si5367 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5367 accepts four clock inputs
ranging from 10 to 707 MHz and generates five
frequency-multiplied clock outputs ranging from 2 kHz
to 945 MHz and select frequencies to 1.4 GHz. The
device provides virtually any frequency translation
combination across this operating range. Independent
dividers are available for every input clock and output
clock, so the Si5367 can accept input clocks at different
frequencies and it can generate output clocks at
different frequencies. The Si5367 input clock frequency
and clock multiplication ratio are programmable through
an I2C or SPI interface. Silicon Laboratories offers a
PC-based software utility, DSPLLsim, that can be used
to determine the optimum PLL divider settings for a
given
input
frequency/clock
multiplication
ratio
combination that minimizes phase noise and power
consumption. This utility can be downloaded from
http://www.silabs.com/timing (click on Documentation).
The Si5367 is based on Silicon Laboratories' 3rd-
generation DSPLL technology, which provides any-
frequency synthesis in a highly integrated PLL solution
that eliminates the need for external VCXO and loop
filter components. The Si5367 PLL loop bandwidth is
digitally programmable and supports a range from
150kHz to 1.3MHz. The DSPLLsim software utility can
be used to calculate valid loop bandwidth settings for a
given input clock frequency/clock multiplication ratio.
The Si5367 monitors all input clocks for loss-of-signal
and provides a LOS alarm when it detects missing
pulses on its inputs.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5367 has five differential clock outputs. The
signal format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize power consumption. In addition, the phase of
each output clock may be adjusted in relation to the
other output clocks. The resolution varies from 800 ps to
2.2 ns depending on the PLL divider settings. Consult
the DSPLLsim configuration software to determine the
phase offset resolution for a given input clock/clock
multiplication
ratio
combination.
For
system-level
debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8
or 2.5 V supply.
3.1. Further Documentation
Consult
the
Silicon
Laboratories
Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5367. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon
Laboratories
has
developed
a
PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
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Si5367A-B-GQ 功能描述:時鐘合成器/抖動清除器 uP-PROGRAMMABE CLK MULT 10 MHZ-1.4 GHZ RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
SI5367A-B-GQR 制造商:Silicon Laboratories Inc 功能描述:
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