tTEMP Max phase changes from –40 to +85 °" />
參數(shù)資料
型號(hào): SI5369-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 3/84頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR SI5369 CLK MULT
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),精密時(shí)鐘
嵌入式:
已用 IC / 零件: Si5369
已供物品: 板,線纜,CD,文檔
Si5369
Rev. 1.0
11
Phase Change due to
Temperature
Variation1
tTEMP
Max phase changes from
–40 to +85 °C
—300
500
ps
PLL Performance
(fin = fout = 622.08 MHz; BW = 7 Hz; LVPECL, XAXB = 114.285 MHz)
Lock Time2
tLOCKMP
Start of ICAL to
of LOL
0.8
1.0
s
Settle Time2
tSETTLE
Start of ICAL to FOUT
within 5 ppm of final value
—4.2
5.0
s
Output Clock Phase
Change
tP_STEP
After clock switch
f3
128 kHz
—200
ps
Closed Loop Jitter
Peaking
JPK
—0.05
0.1
dB
Jitter Tolerance
JTOL
Jitter Frequency
Loop
Bandwidth
5000/BW
ns pk-pk
Phase Noise
fout = 622.08 MHz
CKOPN
100 Hz Offset
–95
dBc/Hz
1 kHz Offset
–110
dBc/Hz
10 kHz Offset
–117
dBc/Hz
100 kHz Offset
–118
dBc/Hz
1 MHz Offset
–131
dBc/Hz
Spurious Noise
SPSPUR
Max spur @ n x F3
(n
1, n x F3 < 100 MHz)
—–67
dBc
Table 3. AC Specifications (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Input to output phase skew after an ICAL is not controlled and can assume any value.
2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit
the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
to submit a technical support request regarding the lock time of your frequency plan.
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