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參數(shù)資料
| 型號(hào)： | SI5369-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 73/84頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR SI5369 CLK MULT |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，精密時(shí)鐘 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | Si5369 |
| 已供物品： | 板，線(xiàn)纜，CD，文檔 |
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Si5369
Rev. 1.0
75
13
57
CS0_C3A
CS1_C4A
I/O
LVCMOS
Input Clock Select/CKIN3 or CKIN4 Active Clock Indicator.
Input: If manual clock selection is chosen, and if
CKSEL_PIN = 1, the CKSEL pins control clock selection and
the CKSEL_REG bits are ignored.
If CKSEL_PIN =0, the CKSEL_REG register bits control this
function and these inputs tristate. If configured as inputs, these
pins must not float.
Output: If auto clock selection is enabled, then they serve as
the CKIN_n active clock indicator.
0 = CKIN3 (CKIN4) is not the active input clock
1 = CKIN3 (CKIN4) is currently the active input to the PLL
The CKn_ACTV_REG bit always reflects the active clock status
for CKIN_n. If CKn_ACTV_PIN = 1, this status will also be
reflected on the CnA pin with active polarity controlled by the
CK_ACTV_POL bit. If CKn_ACTV_PIN = 0, this output tristates.
16
17
XA
XB
IANALOG
External Crystal or Reference Clock.
External crystal should be connected to these pins to use inter-
nal oscillator based reference. Refer to Family Reference Man-
ual for interfacing to an external reference. External reference
must be from a high-quality clock source (TCXO, OCXO). Fre-
quency of crystal or external clock is set by the RATE pins.
29
30
CKIN4+
CKIN4–
IMULTI
Clock Input 4.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN4 serves as the frame sync input associ-
ated with the CKIN2 clock when CK_CONFIG_REG =1.
32
42
RATE0
RATE1
I
3-Level
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crys-
tal or reference clock to be applied to the XA/XB port. Refer to
the Family Reference Manual for settings. These pins have both
a weak pull-up and a weak pull-down; they default to M.
34
35
CKIN2+
CKIN2–
IMULTI
Clock Input 2.
Differential input clock. This input can also be driven with a sin-
gle-ended signal.
39
40
CKIN3+
CKIN3–
IMULTI
Clock Input 3.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN3 serves as the frame sync input associ-
ated with the CKIN1 clock when CK_CONFIG_REG =1.
44
45
CKIN1+
CKIN1–
IMULTI
Clock Input 1.
Differential clock input. This input can also be driven with a sin-
gle-ended signal.
Table 10. Si5369 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5369 Register Map.
CS[1:0]
Active Input Clock
00
CKIN1
01
CKIN2
10
CKIN3
11
CKIN4
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