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參數(shù)資料
| 型號(hào)： | SL28EB740AZIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 14/21頁 |
| 文件大小： | 0K |
| 描述： | IC CLK CK505 TNLCK/TPCLF 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | EProClock® |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:16 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 166.67MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
SL28EB740
DOC#: SP-AP-0006 (Rev. AC)
Page 21 of 21
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-
icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-
sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-
cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Document History Page
Document Title: SL28EB740 PC EProClock Generator for Intel Tunnel Creek & Top Cliff
DOC#: SP-AP-0006 (Rev. AC)
REV.
ECR#
Issue
Date
Orig. of
Change
Description of Change
0.3
11/30/09
JMA
Initial Release
0.4
12/15/09
JMA
Updated Table in Feature section to add PCI clocks
Updated pin naming in pin diagram
Added PCI_STP# state in Table 4
Updated Figure 3 to show trace length
Edited ordering information
AA
1433
01/04/10
JMA
1. Added WOL Support and description
2. Changed VDD_REF pin to VDD_SUSPEND pin
3. Changed PD# pin to WOL_STP# pin
4. Updated Table 4 to show CLKREQ# status
5. Showed Byte 8bit [7:0] to be byte count
6. Added note to Byte 3 bit 4 to indicate bit will not affect CPU clock
7. Added SRC0 to Byte 3 [bit 2 & bit 0] to indicate bit will disable SATA75 and SRC0
8.Updated 12M_48M slew rate to be 2V/ns max
9. Updated Test condition circuit for single-ended clocks from triple loads to double load
10. Updated all differential clocks to be 8V/ns max instead of 4V/ns max
AB
1639
06/23/10
JMA
1. Added CLKIN feature
2. Added Period Spec for CPU, SRC, and DOT96
3. Added Cycle-to-cycle jitter spec for CPU2/SRC5 (ITP clock)
4. Removed REF wording from 14.318MHz
5. Reduced IDD to 130mA from 200mA
6. Reduced PCI clocks cycle-to-cycle jitter to 300ps from 500ps
7. Reduced 25MHzclock cycle-to-cycle jitter to 300ps from 500ps
8. Reduced 48/12MHz clocks cycle-to-cycle jitter to 300ps from 350ps
9. Reduced 14.318MHz clock cycle-to-cycle jitter to 500ps from 1000ps
10. Reduced SATA75 clock cycle-to-cycle jitter to 125ps from 250ps
11. Removed skew for 14MHz
12. Updated CPU2 Cycle-to-cycle jitter to be 125ps from 85ps
13. Removed Prliminary wording
14. Added PD# label to pin configuration on page 1
15. Updated MIL-STD to JEDEC
16. Corrected Pin Configuration diagram for SEL_12_48 to be a pull-up not pull-down
resistor
17. Added period spec for 83.33, 133, and 166MHz
18. Updated block diagram
AC
12/3/10
TRP
1. Updated IIL for clock input
2. Updated foot note
3. Updated Revision ID in Byte7 as ‘0001’
AC
1/11/11
TRP
1. Updated CTCJ max specification for CPU0 and CPU1, DOT96, SRC
2. Removed figure with BSEL input function
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