參數(shù)資料
型號(hào)： SL28EB740AZIT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 3/21頁(yè)
文件大?。?/td> 0K
描述： IC CLK CK505 TNLCK/TPCLF 56TSSOP
標(biāo)準(zhǔn)包裝： 2,000
系列： EProClock®
類型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： Intel CPU 服務(wù)器
輸入： 時(shí)鐘，晶體
輸出： HCSL，LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:16
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 166.67MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
SL28EB740
DOC#: SP-AP-0006 (Rev. AC)
Page 11 of 21
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
PD# (Power down) Assertion
When PD# is sampled LOW by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
LOW. When power down mode is desired as the initial power
on state, PD# must be asserted LOW in less than 10
s after
asserting CKPWRGD.
PD# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300
s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 2 is an example showing the relationship of
clocks coming up.
PD#
USB, 48MHz
DOT96T
DOT96C
SRCT 100MHz
SRCC 100MHz
CPUT, 133MHz
PCI, 33 MHz
REF
CPUC, 133MHz
Figure 1. Power down Assertion Timing Waveform
DOT 9 6 C
PD#
CP UC, 1 3 3 MHz
C P UT , 13 3MH z
S RCC 10 0MH z
U SB, 4 8 MH z
DOT 9 6 T
S RCT 1 0 0 MHz
Ts table
<1 .8 m s
PC I, 3 3 MH z
REF
Td r iv e _ PW R D N #
< 300
s , >2 00m V
Figure 2. Power down Deassertion Timing Waveform
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