參數(shù)資料
型號: SL28EB740AZIT
廠商: Silicon Laboratories Inc
文件頁數(shù): 9/21頁
文件大?。?/td> 0K
描述: IC CLK CK505 TNLCK/TPCLF 56TSSOP
標準包裝: 2,000
系列: EProClock®
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 時鐘,晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:16
差分 - 輸入:輸出: 無/是
頻率 - 最大: 166.67MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
SL28EB740
DOC#: SP-AP-0006 (Rev. AC)
Page 17 of 21
Test and Measurement Set-up
For Single Ended Clocks
The following diagram shows the test load configurations for the single-ended output signals.
48M, 12_48M at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
48MHz Period
Measurement at 1.5V
20.83125
20.83542
ns
TPERIODAbs
48MHz Absolute Period
Measurement at 1.5V
20.48125
21.18542
ns
THIGH
48MHz High time
Measurement at 2V
8.216563
11.15198
ns
TLOW
48MHz Low time
Measurement at 0.8V
7.816563
10.95198
ns
TR / TF (48M) Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
2.0
V/ns
TR / TF
(12_48M)
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
2.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
300
ps
LACC
48M Long Term Accuracy
Measurement at 1.5V
100
ppm
25M at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
39.996
40.004
ns
TPERIODAbs
Absolute Period
Measurement at 1.5V
39.32360
40.67640
ns
TR / TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
300
ps
LACC
25M Long Term Accuracy
Measured at 1.5V
100
ppm
14.318M, at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
69.82033
69.86224
ns
TPERIODAbs
Absolute Period
Measurement at 1.5V
68.83429
70.84826
ns
THIGH
High time
Measurement at 2V
29.97543
38.46654
ns
TLOW
Low time
Measurement at 0.8V
29.57543
38.26654
ns
TR / TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
500
ps
LACC
Long Term Accuracy
Measurement at 1.5V
100
ppm
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
1.8
ms
TSS
Stopclock Set-up Time
10.0
ns
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
Figure 8. Single-ended clocks Single Load Configuration
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